v8_5.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V8_5 is
    generic(DRange : integer := 8);
    port(D   : in  std_logic_vector(DRange - 1 downto 0);
         Q   : out std_logic_vector(DRange - 1 downto 0);
         Clk : in  std_logic);
end V8_5;

architecture A_DFF of V8_5 is
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then 
            for i in D'reverse_range loop
            	if i = Q'left then
            		Q(Q'left) <= D(0);
            	else
            		Q(i) <= D(i + 1);
            	end if;
            end loop;            
        end if;
    end process;
end A_DFF;