v8_9.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V8_9 is
    port(D   : in  std_logic;
         Q   : out std_logic := '0';
         Rst : in  std_logic;
         Clk : in  std_logic);
end V8_9;

architecture A_TDFF of V8_9 is

    component V8_8
    port(D    : in  std_logic;
         Q    : out std_logic := '0';
         Rst  : in  std_logic;
         Clk  : in  std_logic);
    end component;  
           
begin

    UDFF : V8_8
    port map(D   => D   ,
             Q   => Q   ,
             Rst => Rst ,
             Clk => Clk );

end A_TDFF;        

configuration CFG_TDFF of V8_9 is 
    for A_TDFF
        for UDFF : V8_8 use configuration work.CFG_DFF;
        end for;
    end for;
end CFG_TDFF;