v8_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V8_1 is
    generic(setup_time : time := 5 ns);
    port(D   : in  std_logic;
         Q   : out std_logic;
         Clk : in std_logic);
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then
            assert (D'last_event < setup_time) 
            report "setup violation"
            severity error;
        end if;
    end process;
end V8_1;

architecture A_DFF of V8_1 is
    signal Dtime : time;
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then 
            if (D'last_event < setup_time) then
                Q <= 'X';
            else
                Q <= D;
            end if;
            Dtime <= D'last_event;
        end if;
    end process;
end A_DFF;