v8_4.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V8_4 is
    generic(DRange : integer := 8);
    port(D   : in  std_logic_vector(DRange - 1 downto 0);
        Q   : out std_logic_vector(DRange - 1 downto 0);
        Sel  : in  std_logic_vector(1 downto 0);
        LD  : in  std_logic;
        Clk  : in  std_logic);
end V8_4;

architecture A_Counter of V8_4 is
	signal DC0     : std_logic_vector(D'range);
	signal DC1     : std_logic_vector(DC0'range);
	signal DC2     : std_logic_vector(DC1'range);
	signal DC3     : std_logic_vector(DC2'range);
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then
        	if LD = '0' then
        		DC0 <= D;
        		DC1 <= D;
        		DC2 <= D;
        		DC3 <= D;
        	else 
            	DC0 <= DC0 + 1;
            	DC1 <= DC1 + 2;
            	DC2 <= DC2 + 3;
            	DC3 <= DC3 + 4;
            end if;
        end if;
    end process;
    with Sel select
		Q <= DC0 when "00" ,
             DC1 when "01" ,
             DC2 when "10" ,
             DC3 when others;

end A_Counter;