v8_10.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity DFF is
    port(D    : in  std_logic;
         Q    : out std_logic := '0';
         Rst  : in  std_logic;
         Clk  : in  std_logic);
end DFF;

architecture ARDFF of DFF is
begin
    process(Rst,Clk)
    begin
        if Rst = '0' then
            Q <= '0';
        elsif Clk = '1' and Clk'event then 
            Q <= D;
        end if;
    end process;
end ARDFF; 

architecture SRDFF of DFF is
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then
            if Rst = '0' then
                Q <= '0';
            else 
                Q <= D;
            end if;
        end if;
    end process;
end SRDFF;

library ieee;
use ieee.std_logic_1164.all;

entity V8_10 is
    port(D1   : in  std_logic;
         Q1   : out std_logic := '0';
         D2   : in  std_logic;
         Q2   : out std_logic := '0';
         Rst  : in  std_logic;
         Clk  : in  std_logic);
end V8_10;

architecture A_TDFF of V8_10 is

    component DFF
    port(D	 : in  	std_logic;
         Q	 : out 	std_logic := '0';
         Rst : in 	std_logic;
         Clk : in 	std_logic);
    end component;  
           
begin

    UDFF1 : DFF
    port map(D    => D1  ,
             Q    => Q1  ,
             Rst  => Rst ,
             Clk  => Clk );
             
    UDFF2 : DFF
    port map(D    => D2  ,
             Q    => Q2  ,
             Rst  => Rst ,
             Clk  => Clk );

end A_TDFF;         

--configuration CFG_TDFF of TDFF is 
--    for A_TDFF
--        for all : DFF use configuration work.CFG_DFF;
--        end for;
--    end for;
--end CFG_TDFF; 

configuration CFG_TDFF of V8_10 is 
    for A_TDFF
        for UDFF1 : DFF use entity work.DFF(SRDFF);
        end for; 
        for UDFF2 : DFF use entity work.DFF(ARDFF);
        end for;
    end for;
end CFG_TDFF;