v8_3.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V8_3 is
    	generic(DRange : integer := 8);
    	port(D   : in  std_logic_vector(DRange - 1 downto 0);
        	 Q   : out std_logic_vector(DRange - 1 downto 0);
        	 Clk : in  std_logic);
end V8_3;

architecture A_DFF of V8_3 is
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then 
            for i in 0 to D'left - 1 loop
            	Q(i) <= D(i + 1);
            end loop;
            Q(Q'left) <= D(D'right);
        end if;
    end process;
end A_DFF;