v8_0.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V8_0 is
     port(D   : in  std_logic;
          Q   : out std_logic;
          Clk : in  std_logic);
end V8_0;

architecture A_DFF of V8_0 is
begin

    process(Clk)
    begin
        if Clk = '1' and Clk'event then
            Q <= D;
        end if;
   	end process;
   	
end A_DFF;