v11_2.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V11_2 is
   port(b    : in  std_logic;
        a    : out std_logic);
end V11_2;

architecture A_V11_2 of V11_2 is
begin
    a <= '1' after 10 ns when b = '0' else
         '0';

end A_V11_2;