v11_4.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V11_4 is
    port(b   	: in  	std_logic;
         clk 	: in  	std_logic;   
         a   	: out  	std_logic);
end V11_4;

architecture A_V11_4 of V11_4 is
begin
    process
    begin
    	wait until clk = '1' and clk'event;
    		a <= b;
    end process;
end A_V11_4 ;