add4in.vhd

台湾全华科技VHDL教材实例

        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C4_C0_sig , O => C5_C4_N5);
    C5_C4_C1 : XORCY port map ( O => N44 , LI => C5_C4_N5 , CI => C5_N8 
        );
    C5_C4_C2 : MUXCY_L port map ( LO => C5_N12 , S => C5_C4_N5 , DI => 
        N_D3_2 , CI => C5_N8 );
    LUT_C5_C5_C0_sig <= ( N_D3_3 & N_D4_3 );
    C5_C5_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C5_C0_sig , O => C5_C5_N5);
    C5_C5_C1 : XORCY port map ( O => N45 , LI => C5_C5_N5 , CI => C5_N12 
        );
    C5_C5_C2 : MUXCY_L port map ( LO => C5_N16 , S => C5_C5_N5 , DI => 
        N_D3_3 , CI => C5_N12 );
    LUT_C5_C6_C0_sig <= ( N_D3_4 & N_D4_4 );
    C5_C6_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C6_C0_sig , O => C5_C6_N5);
    C5_C6_C1 : XORCY port map ( O => N46 , LI => C5_C6_N5 , CI => C5_N16 
        );
    C5_C6_C2 : MUXCY_L port map ( LO => C5_N20 , S => C5_C6_N5 , DI => 
        N_D3_4 , CI => C5_N16 );
    LUT_C5_C7_C0_sig <= ( N_D3_5 & N_D4_5 );
    C5_C7_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C7_C0_sig , O => C5_C7_N5);
    C5_C7_C1 : XORCY port map ( O => N47 , LI => C5_C7_N5 , CI => C5_N20 
        );
    C5_C7_C2 : MUXCY_L port map ( LO => C5_N24 , S => C5_C7_N5 , DI => 
        N_D3_5 , CI => C5_N20 );
    LUT_C5_C8_C0_sig <= ( N_D3_6 & N_D4_6 );
    C5_C8_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C8_C0_sig , O => C5_C8_N5);
    C5_C8_C1 : XORCY port map ( O => N48 , LI => C5_C8_N5 , CI => C5_N24 
        );
    C5_C8_C2 : MUXCY_L port map ( LO => C5_N28 , S => C5_C8_N5 , DI => 
        N_D3_6 , CI => C5_N24 );
    LUT_C5_C9_C0_sig <= ( N_D3_7 & N_D4_7 );
    C5_C9_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C9_C0_sig , O => C5_C9_N5);
    C5_C9_C1 : XORCY port map ( O => N49 , LI => C5_C9_N5 , CI => C5_N28 
        );
    C5_C9_C2 : MUXCY_L port map ( LO => C5_N32 , S => C5_C9_N5 , DI => 
        N_D3_7 , CI => C5_N28 );
    LUT_C5_C10_C0_sig <= ( N_D3_7 & N_D4_7 );
    C5_C10_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C10_C0_sig , O => C5_C10_N5);
    C5_C10_C1 : XORCY port map ( O => N50 , LI => C5_C10_N5 , CI => C5_N32 
        );
    LUT_C6_C2_C0_sig <= ( SumA_0 & SumB_0 );
    C6_C2_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C2_C0_sig , O => C6_C2_N5);
    C6_C2_C1 : XORCY port map ( O => N96 , LI => C6_C2_N5 , CI => N0 );
    C6_C2_C2 : MUXCY_L port map ( LO => C6_N4 , S => C6_C2_N5 , DI => SumA_0 
        , CI => N0 );
    LUT_C6_C3_C0_sig <= ( SumA_1 & SumB_1 );
    C6_C3_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C3_C0_sig , O => C6_C3_N5);
    C6_C3_C1 : XORCY port map ( O => N97 , LI => C6_C3_N5 , CI => C6_N4 
        );
    C6_C3_C2 : MUXCY_L port map ( LO => C6_N8 , S => C6_C3_N5 , DI => SumA_1 
        , CI => C6_N4 );
    LUT_C6_C4_C0_sig <= ( SumA_2 & SumB_2 );
    C6_C4_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C4_C0_sig , O => C6_C4_N5);
    C6_C4_C1 : XORCY port map ( O => N98 , LI => C6_C4_N5 , CI => C6_N8 
        );
    C6_C4_C2 : MUXCY_L port map ( LO => C6_N12 , S => C6_C4_N5 , DI => 
        SumA_2 , CI => C6_N8 );
    LUT_C6_C5_C0_sig <= ( SumA_3 & SumB_3 );
    C6_C5_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C5_C0_sig , O => C6_C5_N5);
    C6_C5_C1 : XORCY port map ( O => N99 , LI => C6_C5_N5 , CI => C6_N12 
        );
    C6_C5_C2 : MUXCY_L port map ( LO => C6_N16 , S => C6_C5_N5 , DI => 
        SumA_3 , CI => C6_N12 );
    LUT_C6_C6_C0_sig <= ( SumA_4 & SumB_4 );
    C6_C6_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C6_C0_sig , O => C6_C6_N5);
    C6_C6_C1 : XORCY port map ( O => N100 , LI => C6_C6_N5 , CI => C6_N16 
        );
    C6_C6_C2 : MUXCY_L port map ( LO => C6_N20 , S => C6_C6_N5 , DI => 
        SumA_4 , CI => C6_N16 );
    LUT_C6_C7_C0_sig <= ( SumA_5 & SumB_5 );
    C6_C7_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C7_C0_sig , O => C6_C7_N5);
    C6_C7_C1 : XORCY port map ( O => N101 , LI => C6_C7_N5 , CI => C6_N20 
        );
    C6_C7_C2 : MUXCY_L port map ( LO => C6_N24 , S => C6_C7_N5 , DI => 
        SumA_5 , CI => C6_N20 );
    LUT_C6_C8_C0_sig <= ( SumA_6 & SumB_6 );
    C6_C8_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C8_C0_sig , O => C6_C8_N5);
    C6_C8_C1 : XORCY port map ( O => N102 , LI => C6_C8_N5 , CI => C6_N24 
        );
    C6_C8_C2 : MUXCY_L port map ( LO => C6_N28 , S => C6_C8_N5 , DI => 
        SumA_6 , CI => C6_N24 );
    LUT_C6_C9_C0_sig <= ( SumA_7 & SumB_7 );
    C6_C9_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C9_C0_sig , O => C6_C9_N5);
    C6_C9_C1 : XORCY port map ( O => N103 , LI => C6_C9_N5 , CI => C6_N28 
        );
    C6_C9_C2 : MUXCY_L port map ( LO => C6_N32 , S => C6_C9_N5 , DI => 
        SumA_7 , CI => C6_N28 );
    LUT_C6_C10_C0_sig <= ( SumA_8 & SumB_8 );
    C6_C10_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C10_C0_sig , O => C6_C10_N5);
    C6_C10_C1 : XORCY port map ( O => N104 , LI => C6_C10_N5 , CI => C6_N32 
        );
    C6_C10_C2 : MUXCY_L port map ( LO => C6_N36 , S => C6_C10_N5 , DI => 
        SumA_8 , CI => C6_N32 );
    LUT_C6_C11_C0_sig <= ( SumA_8 & SumB_8 );
    C6_C11_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C6_C11_C0_sig , O => C6_C11_N5);
    C6_C11_C1 : XORCY port map ( O => N105 , LI => C6_C11_N5 , CI => C6_N36 
        );
    LUT_C7_C2_C0_sig <= ( N_D1_0 & N_D2_0 );
    C7_C2_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C2_C0_sig , O => C7_C2_N5);
    C7_C2_C1 : XORCY port map ( O => N147 , LI => C7_C2_N5 , CI => N0 );
    C7_C2_C2 : MUXCY_L port map ( LO => C7_N4 , S => C7_C2_N5 , DI => N_D1_0 
        , CI => N0 );
    LUT_C7_C3_C0_sig <= ( N_D1_1 & N_D2_1 );
    C7_C3_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C3_C0_sig , O => C7_C3_N5);
    C7_C3_C1 : XORCY port map ( O => N148 , LI => C7_C3_N5 , CI => C7_N4 
        );
    C7_C3_C2 : MUXCY_L port map ( LO => C7_N8 , S => C7_C3_N5 , DI => N_D1_1 
        , CI => C7_N4 );
    LUT_C7_C4_C0_sig <= ( N_D1_2 & N_D2_2 );
    C7_C4_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C4_C0_sig , O => C7_C4_N5);
    C7_C4_C1 : XORCY port map ( O => N149 , LI => C7_C4_N5 , CI => C7_N8 
        );
    C7_C4_C2 : MUXCY_L port map ( LO => C7_N12 , S => C7_C4_N5 , DI => 
        N_D1_2 , CI => C7_N8 );
    LUT_C7_C5_C0_sig <= ( N_D1_3 & N_D2_3 );
    C7_C5_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C5_C0_sig , O => C7_C5_N5);
    C7_C5_C1 : XORCY port map ( O => N150 , LI => C7_C5_N5 , CI => C7_N12 
        );
    C7_C5_C2 : MUXCY_L port map ( LO => C7_N16 , S => C7_C5_N5 , DI => 
        N_D1_3 , CI => C7_N12 );
    LUT_C7_C6_C0_sig <= ( N_D1_4 & N_D2_4 );
    C7_C6_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C6_C0_sig , O => C7_C6_N5);
    C7_C6_C1 : XORCY port map ( O => N151 , LI => C7_C6_N5 , CI => C7_N16 
        );
    C7_C6_C2 : MUXCY_L port map ( LO => C7_N20 , S => C7_C6_N5 , DI => 
        N_D1_4 , CI => C7_N16 );
    LUT_C7_C7_C0_sig <= ( N_D1_5 & N_D2_5 );
    C7_C7_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C7_C0_sig , O => C7_C7_N5);
    C7_C7_C1 : XORCY port map ( O => N152 , LI => C7_C7_N5 , CI => C7_N20 
        );
    C7_C7_C2 : MUXCY_L port map ( LO => C7_N24 , S => C7_C7_N5 , DI => 
        N_D1_5 , CI => C7_N20 );
    LUT_C7_C8_C0_sig <= ( N_D1_6 & N_D2_6 );
    C7_C8_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C8_C0_sig , O => C7_C8_N5);
    C7_C8_C1 : XORCY port map ( O => N153 , LI => C7_C8_N5 , CI => C7_N24 
        );
    C7_C8_C2 : MUXCY_L port map ( LO => C7_N28 , S => C7_C8_N5 , DI => 
        N_D1_6 , CI => C7_N24 );
    LUT_C7_C9_C0_sig <= ( N_D1_7 & N_D2_7 );
    C7_C9_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C9_C0_sig , O => C7_C9_N5);
    C7_C9_C1 : XORCY port map ( O => N154 , LI => C7_C9_N5 , CI => C7_N28 
        );
    C7_C9_C2 : MUXCY_L port map ( LO => C7_N32 , S => C7_C9_N5 , DI => 
        N_D1_7 , CI => C7_N28 );
    LUT_C7_C10_C0_sig <= ( N_D1_7 & N_D2_7 );
    C7_C10_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C7_C10_C0_sig , O => C7_C10_N5);
    C7_C10_C1 : XORCY port map ( O => N155 , LI => C7_C10_N5 , CI => C7_N32 
        );
    Q_reg_0 : FD port map ( Q => N_Q_0 , D => N96 , C => Clk_BUFGPed );
    Q_reg_1 : FD port map ( Q => N_Q_1 , D => N97 , C => Clk_BUFGPed );
    Q_reg_2 : FD port map ( Q => N_Q_2 , D => N98 , C => Clk_BUFGPed );
    Q_reg_3 : FD port map ( Q => N_Q_3 , D => N99 , C => Clk_BUFGPed );
    Q_reg_4 : FD port map ( Q => N_Q_4 , D => N100 , C => Clk_BUFGPed );
    Q_reg_5 : FD port map ( Q => N_Q_5 , D => N101 , C => Clk_BUFGPed );
    Q_reg_6 : FD port map ( Q => N_Q_6 , D => N102 , C => Clk_BUFGPed );
    Q_reg_7 : FD port map ( Q => N_Q_7 , D => N103 , C => Clk_BUFGPed );
    Q_reg_8 : FD port map ( Q => N_Q_8 , D => N104 , C => Clk_BUFGPed );
    Q_reg_9 : FD port map ( Q => N_Q_9 , D => N105 , C => Clk_BUFGPed );
    SumB_reg_0 : FD port map ( Q => SumB_0 , D => N42 , C => Clk_BUFGPed 
        );
    SumB_reg_1 : FD port map ( Q => SumB_1 , D => N43 , C => Clk_BUFGPed 
        );
    SumB_reg_2 : FD port map ( Q => SumB_2 , D => N44 , C => Clk_BUFGPed 
        );
    SumB_reg_3 : FD port map ( Q => SumB_3 , D => N45 , C => Clk_BUFGPed 
        );
    SumB_reg_4 : FD port map ( Q => SumB_4 , D => N46 , C => Clk_BUFGPed 
        );
    SumB_reg_5 : FD port map ( Q => SumB_5 , D => N47 , C => Clk_BUFGPed 
        );
    SumB_reg_6 : FD port map ( Q => SumB_6 , D => N48 , C => Clk_BUFGPed 
        );
    SumB_reg_7 : FD port map ( Q => SumB_7 , D => N49 , C => Clk_BUFGPed 
        );
    SumB_reg_8 : FD port map ( Q => SumB_8 , D => N50 , C => Clk_BUFGPed 
        );
    SumA_reg_0 : FD port map ( Q => SumA_0 , D => N147 , C => Clk_BUFGPed 
        );
    SumA_reg_1 : FD port map ( Q => SumA_1 , D => N148 , C => Clk_BUFGPed 
        );
    SumA_reg_2 : FD port map ( Q => SumA_2 , D => N149 , C => Clk_BUFGPed 
        );
    SumA_reg_3 : FD port map ( Q => SumA_3 , D => N150 , C => Clk_BUFGPed 
        );
    SumA_reg_4 : FD port map ( Q => SumA_4 , D => N151 , C => Clk_BUFGPed 
        );
    SumA_reg_5 : FD port map ( Q => SumA_5 , D => N152 , C => Clk_BUFGPed 
        );
    SumA_reg_6 : FD port map ( Q => SumA_6 , D => N153 , C => Clk_BUFGPed 
        );
    SumA_reg_7 : FD port map ( Q => SumA_7 , D => N154 , C => Clk_BUFGPed 
        );
    SumA_reg_8 : FD port map ( Q => SumA_8 , D => N155 , C => Clk_BUFGPed 
        );
    C_D1_7 : IBUF port map ( O => N_D1_7 , I => D1(7) );
    C_D1_6 : IBUF port map ( O => N_D1_6 , I => D1(6) );
    C_D1_5 : IBUF port map ( O => N_D1_5 , I => D1(5) );
    C_D1_4 : IBUF port map ( O => N_D1_4 , I => D1(4) );
    C_D1_3 : IBUF port map ( O => N_D1_3 , I => D1(3) );
    C_D1_2 : IBUF port map ( O => N_D1_2 , I => D1(2) );
    C_D1_1 : IBUF port map ( O => N_D1_1 , I => D1(1) );
    C_D1_0 : IBUF port map ( O => N_D1_0 , I => D1(0) );
    C_D2_7 : IBUF port map ( O => N_D2_7 , I => D2(7) );
    C_D2_6 : IBUF port map ( O => N_D2_6 , I => D2(6) );
    C_D2_5 : IBUF port map ( O => N_D2_5 , I => D2(5) );
    C_D2_4 : IBUF port map ( O => N_D2_4 , I => D2(4) );
    C_D2_3 : IBUF port map ( O => N_D2_3 , I => D2(3) );
    C_D2_2 : IBUF port map ( O => N_D2_2 , I => D2(2) );
    C_D2_1 : IBUF port map ( O => N_D2_1 , I => D2(1) );
    C_D2_0 : IBUF port map ( O => N_D2_0 , I => D2(0) );
    C_D3_7 : IBUF port map ( O => N_D3_7 , I => D3(7) );
    C_D3_6 : IBUF port map ( O => N_D3_6 , I => D3(6) );
    C_D3_5 : IBUF port map ( O => N_D3_5 , I => D3(5) );
    C_D3_4 : IBUF port map ( O => N_D3_4 , I => D3(4) );
    C_D3_3 : IBUF port map ( O => N_D3_3 , I => D3(3) );
    C_D3_2 : IBUF port map ( O => N_D3_2 , I => D3(2) );
    C_D3_1 : IBUF port map ( O => N_D3_1 , I => D3(1) );
    C_D3_0 : IBUF port map ( O => N_D3_0 , I => D3(0) );
    C_D4_7 : IBUF port map ( O => N_D4_7 , I => D4(7) );
    C_D4_6 : IBUF port map ( O => N_D4_6 , I => D4(6) );
    C_D4_5 : IBUF port map ( O => N_D4_5 , I => D4(5) );
    C_D4_4 : IBUF port map ( O => N_D4_4 , I => D4(4) );
    C_D4_3 : IBUF port map ( O => N_D4_3 , I => D4(3) );
    C_D4_2 : IBUF port map ( O => N_D4_2 , I => D4(2) );
    C_D4_1 : IBUF port map ( O => N_D4_1 , I => D4(1) );
    C_D4_0 : IBUF port map ( O => N_D4_0 , I => D4(0) );
    C_Q_9 : OBUF_S_12 port map ( O => Q(9) , I => N_Q_9 );
    C_Q_8 : OBUF_S_12 port map ( O => Q(8) , I => N_Q_8 );
    C_Q_7 : OBUF_S_12 port map ( O => Q(7) , I => N_Q_7 );
    C_Q_6 : OBUF_S_12 port map ( O => Q(6) , I => N_Q_6 );
    C_Q_5 : OBUF_S_12 port map ( O => Q(5) , I => N_Q_5 );
    C_Q_4 : OBUF_S_12 port map ( O => Q(4) , I => N_Q_4 );
    C_Q_3 : OBUF_S_12 port map ( O => Q(3) , I => N_Q_3 );
    C_Q_2 : OBUF_S_12 port map ( O => Q(2) , I => N_Q_2 );
    C_Q_1 : OBUF_S_12 port map ( O => Q(1) , I => N_Q_1 );
    C_Q_0 : OBUF_S_12 port map ( O => Q(0) , I => N_Q_0 );
    C108 : BUFGP port map ( O => Clk_BUFGPed , I => Clk );
    C109 : GND port map ( G => N0 );
end FPGA_Express;