add4in.vhd

台湾全华科技VHDL教材实例

-- Synopsys FPGA Express automatically generated file
-- This file will be overwritten by each chip export
-- Author: ahu
-- Program: FPGA Express
-- Version: 3.4.0.5124


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity g_lut is
    -- synopsys template
    generic ( N : integer := 4;
        INIT1 : integer := 1;
        INIT2 : integer := 0;
        INIT3 : integer := 0;
        INIT4 : integer := 0);
    port ( INP : std_logic_vector ( N-1 downto 0 );
        O : out std_logic);
end g_lut;

architecture FPGA_express of g_lut is
begin
    process ( INP )
    variable POS , VAL , I : integer;
    variable INITVAL1 : unsigned(15 downto 0);
    variable INITVAL2 : unsigned((2**N)-1 downto 0);
    variable INITVAL : std_logic_vector((2**N)-1 downto 0);
    begin
        if ( N = 6) then
            INITVAL1 := CONV_UNSIGNED(INIT4 , 16);
            INITVAL(63 downto 48) :=  CONV_STD_LOGIC_VECTOR(INITVAL1, 16);
            INITVAL1 := CONV_UNSIGNED(INIT3 , 16);
            INITVAL(47 downto 32) :=  CONV_STD_LOGIC_VECTOR(INITVAL1, 16);
        end if;
        if ( N >= 5) then
            INITVAL1 := CONV_UNSIGNED(INIT2 , 16);
            INITVAL(31 downto 16) :=  CONV_STD_LOGIC_VECTOR(INITVAL1, 16);
            INITVAL1 := CONV_UNSIGNED(INIT1 , 16);
            INITVAL(15 downto 0) :=  CONV_STD_LOGIC_VECTOR(INITVAL1, 16);
        else
            INITVAL2 := CONV_UNSIGNED(INIT1 , (2 ** N));
            INITVAL :=  CONV_STD_LOGIC_VECTOR(INITVAL2, (2**N));
        end if;
        POS := 0;
        VAL := 1;
        for I in 0 to N-1 loop
            if (INP(I) = '1') then
                POS := POS + VAL;
            end if;
            VAL := VAL * 2;
         end loop;
        O <= INITVAL( POS );
    end process;
end FPGA_Express;

library IEEE;
use IEEE.std_logic_1164.all;

entity XORCY is
    port ( 
        O : out std_logic ;
        LI : in std_logic ;
        CI : in std_logic );
end XORCY ;

architecture FPGA_Express of XORCY is

begin
    O <= ( LI xor CI );
end FPGA_Express;

library IEEE;
use IEEE.std_logic_1164.all;

entity MUXCY_L is
    port ( 
        LO : out std_logic ;
        S : in std_logic ;
        DI : in std_logic ;
        CI : in std_logic );
end MUXCY_L ;

architecture FPGA_Express of MUXCY_L is

    signal net1 , net2 : std_logic ;

begin
    net1 <= ( ( not S ) and DI );
    net2 <= ( S and CI );
    LO <= not ( ( not net1 ) and ( not net2 ) );
end FPGA_Express;

library IEEE;
use IEEE.std_logic_1164.all;

entity FD is
    port ( 
        Q : out std_logic ;
        D : in std_logic ;
        C : in std_logic );
end FD ;

architecture FPGA_Express of FD is

    signal synch_enable : std_logic ;

begin
    process ( C )
    begin
        if ( C'event and C = '1' ) then
        Q <= ( D );
        end if;
    end process;
    synch_enable <= ( '1' );
end FPGA_Express;

library IEEE;
use IEEE.std_logic_1164.all;

entity IBUF is
    port ( 
        O : out std_logic ;
        I : in std_logic );
end IBUF ;

architecture FPGA_Express of IBUF is

begin
    O <= ( I );
end FPGA_Express;

library IEEE;
use IEEE.std_logic_1164.all;

entity OBUF_S_12 is
    port ( 
        O : out std_logic ;
        I : in std_logic );
end OBUF_S_12 ;

architecture FPGA_Express of OBUF_S_12 is

begin
    O <= ( I );
end FPGA_Express;

library IEEE;
use IEEE.std_logic_1164.all;

entity BUFGP is
    port ( 
        O : out std_logic ;
        I : in std_logic );
end BUFGP ;

architecture FPGA_Express of BUFGP is

begin
    O <= ( I );
end FPGA_Express;

library IEEE;
use IEEE.std_logic_1164.all;

entity GND is
    port ( 
        G : out std_logic );
end GND ;

architecture FPGA_Express of GND is

begin
    G <= not ( '1' );
end FPGA_Express;

library IEEE;
use IEEE.std_logic_1164.all;

entity Add4In is
    port ( 
        D1 : in std_logic_vector (7 downto 0) ;
        D2 : in std_logic_vector (7 downto 0) ;
        D3 : in std_logic_vector (7 downto 0) ;
        D4 : in std_logic_vector (7 downto 0) ;
        Q : out std_logic_vector (9 downto 0) ;
        Clk : in std_logic );
end Add4In ;

architecture FPGA_Express of Add4In is

    component g_lut
        generic ( N : integer;
            INIT1 : integer;
            INIT2 : integer;
            INIT3 : integer;
            INIT4 : integer);
        port ( INP : std_logic_vector ( N-1 downto 0 );
            O : out std_logic);
    end component;
    
    component XORCY
        port ( 
            O : out std_logic ;
            LI : in std_logic ;
            CI : in std_logic );
    end component;
    
    component MUXCY_L
        port ( 
            LO : out std_logic ;
            S : in std_logic ;
            DI : in std_logic ;
            CI : in std_logic );
    end component;
    
    component FD
        port ( 
            Q : out std_logic ;
            D : in std_logic ;
            C : in std_logic );
    end component;
    
    component IBUF
        port ( 
            O : out std_logic ;
            I : in std_logic );
    end component;
    
    component OBUF_S_12
        port ( 
            O : out std_logic ;
            I : in std_logic );
    end component;
    
    component BUFGP
        port ( 
            O : out std_logic ;
            I : in std_logic );
    end component;
    
    component GND
        port ( 
            G : out std_logic );
    end component;
    
    signal N_D1_7 , N_D1_6 , N_D1_5 , N_D1_4 , N_D1_3 , N_D1_2 , N_D1_1 
        , N_D1_0 , N_D2_7 , N_D2_6 , N_D2_5 , N_D2_4 , N_D2_3 , N_D2_2 
        , N_D2_1 , N_D2_0 , N_D3_7 , N_D3_6 , N_D3_5 , N_D3_4 , N_D3_3 
        , N_D3_2 , N_D3_1 , N_D3_0 , N_D4_7 , N_D4_6 , N_D4_5 , N_D4_4 
        , N_D4_3 , N_D4_2 , N_D4_1 , N_D4_0 , N_Q_9 , N_Q_8 , N_Q_7 , N_Q_6 
        , N_Q_5 , N_Q_4 , N_Q_3 , N_Q_2 , N_Q_1 , N_Q_0 , Clk_BUFGPed , 
        SumA_8 , SumA_7 , SumA_6 , SumA_5 , SumA_4 , SumA_3 , SumA_2 , 
        SumA_1 , SumA_0 , SumB_8 , SumB_7 , SumB_6 , SumB_5 , SumB_4 , 
        SumB_3 , SumB_2 , SumB_1 , SumB_0 , N0 , N42 , N43 , N44 , N45 
        , N46 , N47 , N48 , N49 , N50 , N96 , N97 , N98 , N99 , N100 , 
        N101 , N102 , N103 , N104 , N105 , N147 , N148 , N149 , N150 , 
        N151 , N152 , N153 , N154 , N155 , C5_N4 , C5_N8 , C5_N12 , C5_N16 
        , C5_N20 , C5_N24 , C5_N28 , C5_N32 , C6_N4 , C6_N8 , C6_N12 , 
        C6_N16 , C6_N20 , C6_N24 , C6_N28 , C6_N32 , C6_N36 , C7_N4 , C7_N8 
        , C7_N12 , C7_N16 , C7_N20 , C7_N24 , C7_N28 , C7_N32 , C5_C2_N5 
        , C5_C3_N5 , C5_C4_N5 , C5_C5_N5 , C5_C6_N5 , C5_C7_N5 , C5_C8_N5 
        , C5_C9_N5 , C5_C10_N5 , C6_C2_N5 , C6_C3_N5 , C6_C4_N5 , C6_C5_N5 
        , C6_C6_N5 , C6_C7_N5 , C6_C8_N5 , C6_C9_N5 , C6_C10_N5 , C6_C11_N5 
        , C7_C2_N5 , C7_C3_N5 , C7_C4_N5 , C7_C5_N5 , C7_C6_N5 , C7_C7_N5 
        , C7_C8_N5 , C7_C9_N5 , C7_C10_N5 : std_logic ;
    signal LUT_C5_C2_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C5_C3_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C5_C4_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C5_C5_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C5_C6_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C5_C7_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C5_C8_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C5_C9_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C5_C10_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C2_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C3_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C4_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C5_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C6_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C7_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C8_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C9_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C10_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C6_C11_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C2_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C3_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C4_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C5_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C6_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C7_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C8_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C9_C0_sig : std_logic_vector ( 1 downto 0 );
    signal LUT_C7_C10_C0_sig : std_logic_vector ( 1 downto 0 );

begin
    LUT_C5_C2_C0_sig <= ( N_D3_0 & N_D4_0 );
    C5_C2_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C2_C0_sig , O => C5_C2_N5);
    C5_C2_C1 : XORCY port map ( O => N42 , LI => C5_C2_N5 , CI => N0 );
    C5_C2_C2 : MUXCY_L port map ( LO => C5_N4 , S => C5_C2_N5 , DI => N_D3_0 
        , CI => N0 );
    LUT_C5_C3_C0_sig <= ( N_D3_1 & N_D4_1 );
    C5_C3_C0 : g_lut
        generic map ( N => 2 , INIT1 => 6 , INIT2 => 0 , INIT3 => 0 , INIT4 
        => 0)
        port map ( INP => LUT_C5_C3_C0_sig , O => C5_C3_N5);
    C5_C3_C1 : XORCY port map ( O => N43 , LI => C5_C3_N5 , CI => C5_N4 
        );
    C5_C3_C2 : MUXCY_L port map ( LO => C5_N8 , S => C5_C3_N5 , DI => N_D3_1 
        , CI => C5_N4 );
    LUT_C5_C4_C0_sig <= ( N_D3_2 & N_D4_2 );
    C5_C4_C0 : g_lut