v11_3.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity XCond is
   port(rst    : in  std_logic;
        clk    : in  std_logic;
        a      : out std_logic);
end XCond;

architecture A_XCond of XCond is
begin
    process(rst,clk)
    begin
		if rst = '0' then
			a <= '0';
		elsif clk = '1' and clk'event then
			a <= '1';
		else
			a <= '0';
		end if;
    end process;
end A_XCond;