v11_5.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V11_5 is
    port(b   : in  	std_logic;
         clk : in  	std_logic;  
         rst : in  	std_logic;   
         a   : out  std_logic);
end V11_5;

architecture A_V11_5 of V11_5 is
begin
    process(rst,clk)
    begin
    	if rst = '0' then
    		a <= '0';
    	elsif clk = '1' and clk'event then
    		a <= b;
    	end if;
    end process;
end  A_V11_5 ;