v9_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity GenericTest is
  port(DInA		: in std_logic_vector(7 downto 0);
      DInB		: in std_logic_vector(7 downto 0);
      DInC		: in std_logic_vector(7 downto 0);
      DInD		: in std_logic_vector(7 downto 0);
      DOut		: out std_logic_vector(9 downto 0));
end GenericTest;

architecture A of GenericTest is

	component Adder8
	  port(AIn     : in std_logic_vector(7 downto 0);
	      BIn     : in std_logic_vector(7 downto 0);
	      DOut    : out std_logic_vector(8 downto 0));
	end component;

	component Adder9
	  port(AIn     : in std_logic_vector(8 downto 0);
	      BIn     : in std_logic_vector(8 downto 0);
	      DOut    : out std_logic_vector(9 downto 0));
	end component;
	
	signal DTempA : std_logic_vector(8 downto 0);
	signal DTempB : std_logic_vector(8 downto 0);
	
begin

	U1 : Adder8
	   port map( AIn    => DInA    ,
	           BIn    => DInB    ,
	           DOut   => DTempA  );

	U2 : Adder8
	  port map (AIn    => DInC    ,
	           BIn    => DInD    ,
	           DOut   => DTempB  );

	U3 : Adder9
	  port map( AIn    => DTempA    ,
	           BIn    => DTempB    ,
	           DOut   => DOut      );

end A;