v6_4.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V6_4 is 
	port(Sel     : in  std_logic_vector(3 downto 0);
	     Ina	 : in  std_logic;
	     Inb	 : in  std_logic;
	     Inc	 : in  std_logic;
	     Ind	 : in  std_logic;
	     Ine	 : in  std_logic;	     
	     Clk     : in  std_logic;
	     Reset   : in  std_logic;
	     OutD    : out std_logic);
end V6_4;

architecture A of V6_4 is
	
	signal Inao : std_logic;
	signal Inbo : std_logic;
	signal Inco : std_logic;
	signal Indo : std_logic;

begin
	process(Reset,Clk)
	begin
		if Reset = '0' then
			OutD <= '0';
		elsif Clk = '1' and Clk'event then
			if Sel(3) = '0' then
				Inao <= Ina; 
				OutD <= Ina;
			elsif Sel(2) = '0' and Inao = '0' then
				Inbo <= Inb; 
				OutD <= Inb;
			elsif Sel(1) = '0' and Inbo = '0' then
				Inco <= Inc; 
				OutD <= Inc;
			elsif Sel(0) = '0' and Inco = '0' then
				Indo <= Ind; 
				OutD <= Ind;
			elsif Indo = '0' then 
				OutD <= Ine; 
			end if;
		end if;
	end process;
end A;