v6_8.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.ALL;

entity V6_8 is
 port(Reset   : in  std_logic;
      Din	 : in std_logic;
      Dout	 : out std_logic);
end V6_8;

architecture a_clk of V6_8 is 

begin

	process
	begin
		wait on reset;
			Dout <= Din;
	end process;
	
end a_clk;