v6_15.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity loopexit is
 port(Din	: in  std_logic_vector(7 downto 0);
      Error	: out  boolean;
      Reset : in  std_logic; 
      DStb  : in  std_logic);
end loopexit;

architecture a_loopexit of loopexit is 

	type DArray is array(0 to 9) of std_logic_vector(7 downto 0);
	signal DinArray : DArray;
	signal DInCount : integer range 0 to 16;
	signal Start    : std_logic;

begin

	process(Reset,Start)
		variable SCount   : integer range 0 to 11;
	begin
		if Reset = '0' then
			Error <= false;
		elsif Start = '0' then
			SCount := 0;
			for i in 0 to 9 loop
				if DinArray(i) = 0 then
					Error <= true;
					exit;
				end if;
				SCount := SCount + 1;
				Error <= false;
			end loop;
		end if;
	end process;
	
	process(Reset,DStb)
	begin
		if Reset = '0' then
			DinCount <= 0;
			Start <= '1';
		elsif DStb = '1' and DStb'event then
			if DinCount < 9 then
				DinCount <= DinCount + 1;
			else
				DinCount <= 0;
			end if;
			if DinCount < 9 then
				Start <= '1';
			else
				Start <= '0';
			end if;
		end if;
	end process;
	
	process(Reset,DStb)
	begin
		if Reset = '0' then
			for i in 0 to 9 loop
				DinArray(i) <= "00000000";
			end loop;
		elsif DStb = '0' and DStb'event then
			DinArray(DinCount) <= Din;
		end if;
	end process;  
	
end a_loopexit;