v6_16.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 48 行

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.std_logic_arith.ALL;
use std.textio.all;

entity testnote is
 port(Start		: in  std_logic;
      DataOut 	: out std_logic_vector(7 downto 0);
      Reset		: in  std_logic;
      Clk   	: in  std_logic);
end testnote;

architecture a_testnote of testnote is 
	
begin

	process(Start,Clk)
	    file    f       : TEXT open read_mode is "text.dat";
		variable inline   : line;
		variable buf     : integer; 
		variable i       : integer := 0;
		variable j       : integer := 0;
	begin
		if Reset = '0' then
			DataOut <= "00000000";
		elsif Clk = '1' and Clk'event then
			if Start = '0' then
				if not Endfile(f) then	
					readline(f,inline);	
	    			read(inline, buf);
	    		end if;
	    		DataOut <= CONV_STD_LOGIC_VECTOR(buf,8);
				assert j < 9 
				report "Every 10 Data Output"
				severity NOTE;
				if j < 9 then
					j := j + 1;
				else
					i := i + 1;
					j := 0;
				end if; 
			end if;
		end if;
	end process;
		
end a_testnote;