v6_14.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity loopnext is
 port(ScoreIn  : in  integer;
      PassOut  : out integer;
      FailOut  : out integer;
      Reset    : in  std_logic;   
      SheetIn  : in  std_logic);
end loopnext;

architecture a_loopnext of loopnext is 

    constant PassScore : integer := 90;
	type   SArray is array(0 to 10) of integer; 
    signal DCount : integer := 0;
    signal SCore : SArray;

begin

	process(Reset,SheetIn)
    	variable PassCount : integer := 0;
    	variable FailCount : integer := 0;
	begin
		if Reset = '0' then
			PassCount := 0;
			FailCount := 0;
			PassOut <= 0;
			FailOut <= 0;
		elsif SheetIn = '1' and SheetIn'event then
		    if DCount = 10 then
				for i in 0 to 9 loop
					if SCore(i) > PassScore then
     					PassCount := PassCount + 1;
						next;
					end if;
					FailCount := FailCount + 1;
				end loop;
				PassOut <= PassCount;
				FailOut <= FailCount;
			end if;
		end if;
	end process;
	
	process(Reset,SheetIn)
	begin
		if Reset = '0' then
			DCount <= 0;
		elsif SheetIn = '0' and SheetIn'event then
			if DCount = 10 then
				DCount <= 0;
			else
				DCount <= DCount + 1;
			end if;
			SCore(DCount) <= ScoreIn;
		end if;
	end process;
		
end a_loopnext;