v6_0.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V6_0 is
	port(rst     : in  std_logic;
	     clk     : in  std_logic;
	     d       : in  std_logic;
	     ce      : in  std_logic;
		 q       : out std_logic);
end V6_0;

architecture behav of V6_0 is
		
begin
	
	ARstDFF : process(rst,clk) 
			  begin
				if rst = '0' then
					q <= '0';
				elsif clk = '1' and clk'event then
					if ce = '0' then
						q <= d;
 					end if;
 			    end if;
			  end process ARstDFF;
	
end behav;