v6_10.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V6_10 is
	port(clk  : in std_logic;
	     rst  : in std_logic;
	     d    : in std_logic;
	     q    : out std_logic);
end V6_10;

architecture A of V6_10 is
begin

	--process(clk)
	--begin
	--	if clk = '1' and clk'event then
	--		if rst = '0' then
	--			q <= '0';
	--		else
	--			q <= d;
	--		end if;
	--	end if;
	--end process;
	
	process
	begin
		wait until clk = '1' and clk'event ;
			if rst = '0' then
				q <= '0';
			else
				q <= d;
			end if;
	end process;

	
end A;