v6_6.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.ALL;

entity V6_6 is
    port(clkout	: out std_logic);
end V6_6;

architecture a_clk of V6_6 is
	signal clk_int : std_logic := '0';
begin

	process
	begin
		wait for 10 ns;
			clk_int <= not clk_int;
	end process;
	
	clkout <= clk_int;
	
end a_clk;