v6_2.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V6_2 is 
	 port(a	    : in  std_logic;
	     b	    : in  std_logic;
	     Clk1   : in  std_logic;
	     Clk2   : in  std_logic;
	     o      : out std_logic);
end V6_2;

architecture A of V6_2 is
begin
	process(Clk1,Clk2)
	begin
		if Clk1 = '1' and Clk1'event then
			o <= a;
		elsif Clk2 = '1' and Clk2'event then
			o <= b;
		end if;
	end process;
end A;