v6_9.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V6_9 is
end V6_9;

architecture A of V6_9 is

    signal reset : std_logic;
    signal Out1  : std_logic := '1';
    signal Out2  : std_logic := '0';

begin
    
    process
    begin
        wait on reset;
            Out1 <= not Out1 after 5 ns;
    end process;
    
    Out2 <= reset after 5 ns;
    
end A;