v6_11.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity loop1 is
 port(Din		: in  std_logic_vector(7 downto 0);
     Dout	: out  std_logic_vector(7 downto 0);
     Reset  : in  std_logic;     
     Clk    : in  std_logic);
end loop1;

architecture a_loop1 of loop1 is 

begin

	process(Reset,Clk)
		variable count : integer range 0 to 7;
	begin
		if Reset = '0' then
			Dout <= "00000000";
		elsif Clk = '1' and Clk'event then
			count := 0;
			Dout(7) <= Din(0);
			while (count < 7) loop
				Dout(count) <= Din(count + 1);
				count := count + 1;
			end loop;
		end if;
	end process;
	
end a_loop1;