v6_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V6_1 is 
	 port(Ina	 : in  std_logic;
	      Clk    : in  std_logic;
	      OutD   : out std_logic);
end V6_1;

architecture A of V6_1 is

	signal Reg1   : std_logic;
	signal Reg2   : std_logic;
	signal Reg3   : std_logic;

begin
	process
	begin
		wait until Clk = '1' and Clk'event;
			Reg1 <= Ina;
			Reg2 <= Reg1;
			Reg3 <= Reg2;
			OutD <= Reg3;
	end process;
end A;