v13_0.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity Add4In is
    port(D1  : in   std_logic_vector(7 downto 0);
         D2  : in   std_logic_vector(7 downto 0);
         D3  : in   std_logic_vector(7 downto 0);
         D4  : in   std_logic_vector(7 downto 0);
         Q   : out  std_logic_vector(9 downto 0);
         Clk : in   std_logic);
end Add4In;

architecture A_Add4In of Add4In is
	signal SumA : std_logic_vector(8 downto 0);
	signal SumB : std_logic_vector(8 downto 0);
begin
    process(Clk)
    begin
        if Clk = '1' and Clk'event then
        	SumA <= (D1(D1'left) & D1) + (D2(D2'left) & D2);
        	SumB <= (D3(D3'left) & D3) + (D4(D4'left) & D4);
        	Q <= (SumA(SumA'left) & SumA) + 
                 (SumB(SumB'left) & SumB);
        end if;
    end process;
end  A_Add4In ;