time_sim.vhd

台湾全华科技VHDL教材实例

-- Xilinx Vhdl produced by program ngd2vhdl C.18
-- Command: -w FltAdder.nga time_sim.vhd 
-- Options: -w -ti UUT 
-- Date: Wed Jun 21 23:03:43 2000 
-- Input file: FltAdder.nga
-- Output file: time_sim.vhd
-- Tmp file: C:/WINDOWS/TEMP/xil_6
-- Design name: FltAdder
-- Xilinx: E:/fndtn
-- # of Entities: 1
-- Device: v50pq240-4

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity FLTADDER is 
  port (
    CLK : in STD_LOGIC := 'X'; 
    DINB : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    DINA : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end FLTADDER;

architecture STRUCTURE of FLTADDER is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal C98_IBUFG : STD_LOGIC; 
  signal CLK_BUFGPED : STD_LOGIC; 
  signal UFLT2FIX_C320_C4_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N468 : STD_LOGIC; 
  signal UFLT2FIX_N469 : STD_LOGIC; 
  signal UFLT2FIX_C320_C6_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N470 : STD_LOGIC; 
  signal UFLT2FIX_N471 : STD_LOGIC; 
  signal UFLT2FIX_C320_C8_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N472 : STD_LOGIC; 
  signal UFLT2FIX_N473 : STD_LOGIC; 
  signal UFLT2FIX_C320_C10_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N474 : STD_LOGIC; 
  signal UFLT2FIX_N475 : STD_LOGIC; 
  signal UFLT2FIX_C320_C12_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N476 : STD_LOGIC; 
  signal UFLT2FIX_N477 : STD_LOGIC; 
  signal UFLT2FIX_C320_C14_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N478 : STD_LOGIC; 
  signal UFLT2FIX_N479 : STD_LOGIC; 
  signal UFLT2FIX_C320_C16_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N480 : STD_LOGIC; 
  signal UFLT2FIX_N481 : STD_LOGIC; 
  signal UFLT2FIX_C320_C18_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N482 : STD_LOGIC; 
  signal UFLT2FIX_N483 : STD_LOGIC; 
  signal UFLT2FIX_C320_C20_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N484 : STD_LOGIC; 
  signal UFLT2FIX_N485 : STD_LOGIC; 
  signal UFLT2FIX_C320_C22_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N486 : STD_LOGIC; 
  signal UFLT2FIX_N487 : STD_LOGIC; 
  signal UFLT2FIX_C320_C24_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N488 : STD_LOGIC; 
  signal UFLT2FIX_N489 : STD_LOGIC; 
  signal UFLT2FIX_N490 : STD_LOGIC; 
  signal UFLT2FIX_N491 : STD_LOGIC; 
  signal UFLT2FIX_C321_C4_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N647 : STD_LOGIC; 
  signal UFLT2FIX_N648 : STD_LOGIC; 
  signal UFLT2FIX_C321_C6_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N649 : STD_LOGIC; 
  signal UFLT2FIX_N650 : STD_LOGIC; 
  signal UFLT2FIX_C321_C8_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N651 : STD_LOGIC; 
  signal UFLT2FIX_N652 : STD_LOGIC; 
  signal UFLT2FIX_C321_C10_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N653 : STD_LOGIC; 
  signal UFLT2FIX_N654 : STD_LOGIC; 
  signal UFLT2FIX_C321_C12_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N655 : STD_LOGIC; 
  signal UFLT2FIX_N656 : STD_LOGIC; 
  signal UFLT2FIX_C321_C14_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N657 : STD_LOGIC; 
  signal UFLT2FIX_N658 : STD_LOGIC; 
  signal UFLT2FIX_C321_C16_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N659 : STD_LOGIC; 
  signal UFLT2FIX_N660 : STD_LOGIC; 
  signal UFLT2FIX_C321_C18_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N661 : STD_LOGIC; 
  signal UFLT2FIX_N662 : STD_LOGIC; 
  signal UFLT2FIX_C321_C20_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N663 : STD_LOGIC; 
  signal UFLT2FIX_N664 : STD_LOGIC; 
  signal UFLT2FIX_C321_C22_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N665 : STD_LOGIC; 
  signal UFLT2FIX_N666 : STD_LOGIC; 
  signal UFLT2FIX_C321_C24_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N667 : STD_LOGIC; 
  signal UFLT2FIX_N668 : STD_LOGIC; 
  signal UFLT2FIX_N669 : STD_LOGIC; 
  signal UFLT2FIX_N670 : STD_LOGIC; 
  signal UFLT2FIX_C322_C3_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N1355 : STD_LOGIC; 
  signal UFLT2FIX_N1357 : STD_LOGIC; 
  signal UFLT2FIX_C322_C5_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N1359 : STD_LOGIC; 
  signal UFLT2FIX_N1361 : STD_LOGIC; 
  signal UFLT2FIX_C322_C7_C1_O : STD_LOGIC; 
  signal UFLT2FIX_N1363 : STD_LOGIC; 
  signal UFLT2FIX_N1365 : STD_LOGIC; 
  signal UFLT2FIX_N688 : STD_LOGIC; 
  signal UFLT2FIX_N1367 : STD_LOGIC; 
  signal UFLT2FIX_N1369 : STD_LOGIC; 
  signal UADDER_C18_C3_C2_O : STD_LOGIC; 
  signal MANB_0_Q : STD_LOGIC; 
  signal MANB_1_Q : STD_LOGIC; 
  signal UADDER_N116 : STD_LOGIC; 
  signal UADDER_N117 : STD_LOGIC; 
  signal UADDER_C18_C5_C2_O : STD_LOGIC; 
  signal MANB_2_Q : STD_LOGIC; 
  signal MANB_3_Q : STD_LOGIC; 
  signal UADDER_N118 : STD_LOGIC; 
  signal UADDER_N119 : STD_LOGIC; 
  signal UADDER_C18_C7_C2_O : STD_LOGIC; 
  signal MANB_4_Q : STD_LOGIC; 
  signal MANB_5_Q : STD_LOGIC; 
  signal UADDER_N120 : STD_LOGIC; 
  signal UADDER_N121 : STD_LOGIC; 
  signal UADDER_C18_C9_C2_O : STD_LOGIC; 
  signal MANB_6_Q : STD_LOGIC; 
  signal MANB_7_Q : STD_LOGIC; 
  signal UADDER_N122 : STD_LOGIC; 
  signal UADDER_N123 : STD_LOGIC; 
  signal UADDER_C18_C11_C2_O : STD_LOGIC; 
  signal MANB_8_Q : STD_LOGIC; 
  signal MANB_9_Q : STD_LOGIC; 
  signal UADDER_N124 : STD_LOGIC; 
  signal UADDER_N125 : STD_LOGIC; 
  signal UADDER_C18_C13_C2_O : STD_LOGIC; 
  signal MANB_10_Q : STD_LOGIC; 
  signal UFLT2FIX_SYN3141 : STD_LOGIC; 
  signal UFLT2FIX_SYN8456 : STD_LOGIC; 
  signal UADDER_N126 : STD_LOGIC; 
  signal UADDER_N127 : STD_LOGIC; 
  signal UADDER_C18_C15_C2_O : STD_LOGIC; 
  signal MANB_12_Q : STD_LOGIC; 
  signal MANB_13_Q : STD_LOGIC; 
  signal UADDER_N128 : STD_LOGIC; 
  signal UADDER_N129 : STD_LOGIC; 
  signal UADDER_C18_C17_C2_O : STD_LOGIC; 
  signal MANB_14_Q : STD_LOGIC; 
  signal MANB_15_Q : STD_LOGIC; 
  signal UADDER_N130 : STD_LOGIC; 
  signal UADDER_N131 : STD_LOGIC; 
  signal UADDER_C18_C19_C2_O : STD_LOGIC; 
  signal UFLT2FIX_SYN2416 : STD_LOGIC; 
  signal UFLT2FIX_SYN3053 : STD_LOGIC; 
  signal UFLT2FIX_SYN9466 : STD_LOGIC; 
  signal MANB_17_Q : STD_LOGIC; 
  signal UADDER_N132 : STD_LOGIC; 
  signal UADDER_N133 : STD_LOGIC; 
  signal UADDER_C18_C21_C2_O : STD_LOGIC; 
  signal MANB_18_Q : STD_LOGIC; 
  signal MANB_19_Q : STD_LOGIC; 
  signal UADDER_N134 : STD_LOGIC; 
  signal UADDER_N135 : STD_LOGIC; 
  signal UADDER_C18_C23_C2_O : STD_LOGIC; 
  signal MANB_20_Q : STD_LOGIC; 
  signal MANB_21_Q : STD_LOGIC; 
  signal UADDER_N136 : STD_LOGIC; 
  signal UADDER_N137 : STD_LOGIC; 
  signal UADDER_C18_C25_C2_O : STD_LOGIC; 
  signal MANB_22_Q : STD_LOGIC; 
  signal UFLT2FIX_SYN2934 : STD_LOGIC; 
  signal UFLT2FIX_SYN9347 : STD_LOGIC; 
  signal UADDER_N138 : STD_LOGIC; 
  signal UADDER_N139 : STD_LOGIC; 
  signal UADDER_C18_C26_N5 : STD_LOGIC; 
  signal UADDER_N140 : STD_LOGIC; 
  signal UFIX2FLT_C564_C3_C2_O : STD_LOGIC; 
  signal UFIX2FLT_N493 : STD_LOGIC; 
  signal UFIX2FLT_N494 : STD_LOGIC; 
  signal UFIX2FLT_C564_C5_C2_O : STD_LOGIC; 
  signal UFIX2FLT_N495 : STD_LOGIC; 
  signal UFIX2FLT_N496 : STD_LOGIC; 
  signal UFIX2FLT_C564_C7_C2_O : STD_LOGIC; 
  signal UFIX2FLT_N497 : STD_LOGIC; 
  signal UFIX2FLT_N498 : STD_LOGIC; 
  signal UFIX2FLT_N499 : STD_LOGIC; 
  signal UFIX2FLT_N500 : STD_LOGIC; 
  signal UFLT2FIX_C318_C4_C2_O : STD_LOGIC; 
  signal UFLT2FIX_N304 : STD_LOGIC; 
  signal UFLT2FIX_N278 : STD_LOGIC; 
  signal UFLT2FIX_C318_C6_C2_O : STD_LOGIC; 
  signal UFLT2FIX_N279 : STD_LOGIC; 
  signal UFLT2FIX_N280 : STD_LOGIC; 
  signal UFLT2FIX_C318_C8_C2_O : STD_LOGIC; 
  signal UFLT2FIX_N281 : STD_LOGIC; 
  signal UFLT2FIX_N282 : STD_LOGIC; 
  signal UFLT2FIX_N283 : STD_LOGIC; 
  signal UFLT2FIX_N284 : STD_LOGIC; 
  signal UFIX2FLT_C557_C4_C2_O : STD_LOGIC; 
  signal UFIX2FLT_C706 : STD_LOGIC; 
  signal UFIX2FLT_SYN1160 : STD_LOGIC; 
  signal UFIX2FLT_SYN2743 : STD_LOGIC; 
  signal UFIX2FLT_SYN2749 : STD_LOGIC; 
  signal UFIX2FLT_SYN5871 : STD_LOGIC; 
  signal UFIX2FLT_N171 : STD_LOGIC; 
  signal UFIX2FLT_N172 : STD_LOGIC; 
  signal UFIX2FLT_C557_C6_C2_O : STD_LOGIC; 
  signal UFIX2FLT_SYN2852 : STD_LOGIC; 
  signal UFIX2FLT_SYN5857 : STD_LOGIC; 
  signal UFIX2FLT_SYN6301 : STD_LOGIC; 
  signal UFIX2FLT_SYN2930 : STD_LOGIC; 
  signal UFIX2FLT_SYN5839 : STD_LOGIC; 
  signal UFIX2FLT_SYN5842 : STD_LOGIC; 
  signal UFIX2FLT_N173 : STD_LOGIC; 
  signal UFIX2FLT_N174 : STD_LOGIC; 
  signal UFIX2FLT_C557_C8_C2_O : STD_LOGIC; 
  signal UFIX2FLT_SYN1164 : STD_LOGIC; 
  signal UFIX2FLT_SYN5826 : STD_LOGIC; 
  signal UFIX2FLT_N175 : STD_LOGIC; 
  signal UFIX2FLT_N176 : STD_LOGIC; 
  signal UFIX2FLT_N177 : STD_LOGIC; 
  signal UFIX2FLT_N178 : STD_LOGIC; 
  signal UFLT2FIX_C319_C4_C2_O : STD_LOGIC; 
  signal UFLT2FIX_N277 : STD_LOGIC; 
  signal UFLT2FIX_N305 : STD_LOGIC; 
  signal UFLT2FIX_C319_C6_C2_O : STD_LOGIC; 
  signal UFLT2FIX_N306 : STD_LOGIC; 
  signal UFLT2FIX_N307 : STD_LOGIC; 
  signal UFLT2FIX_C319_C8_C2_O : STD_LOGIC; 
  signal UFLT2FIX_N308 : STD_LOGIC; 
  signal UFLT2FIX_N309 : STD_LOGIC; 
  signal UFLT2FIX_N310 : STD_LOGIC; 
  signal UFLT2FIX_N311 : STD_LOGIC; 
  signal UFIX2FLT_C578_C4_C1_O : STD_LOGIC; 
  signal UFIX2FLT_N1783 : STD_LOGIC; 
  signal UFIX2FLT_N1785 : STD_LOGIC; 
  signal UFIX2FLT_N1248 : STD_LOGIC; 
  signal UFIX2FLT_N1249 : STD_LOGIC; 
  signal UFIX2FLT_C578_C6_C1_O : STD_LOGIC; 
  signal UFIX2FLT_N1787 : STD_LOGIC; 
  signal UFIX2FLT_N1789 : STD_LOGIC; 
  signal UFIX2FLT_N1250 : STD_LOGIC; 
  signal UFIX2FLT_N1251 : STD_LOGIC; 
  signal UFIX2FLT_C578_C8_C1_O : STD_LOGIC; 
  signal UFIX2FLT_N1791 : STD_LOGIC; 
  signal UFIX2FLT_N1793 : STD_LOGIC; 
  signal UFIX2FLT_N1252 : STD_LOGIC; 
  signal UFIX2FLT_N1253 : STD_LOGIC; 
  signal UFIX2FLT_C578_C10_C1_O : STD_LOGIC; 
  signal UFIX2FLT_N1795 : STD_LOGIC; 
  signal UFIX2FLT_N1797 : STD_LOGIC; 
  signal UFIX2FLT_N1254 : STD_LOGIC; 
  signal UFIX2FLT_N1255 : STD_LOGIC; 
  signal UFIX2FLT_C578_C12_C1_O : STD_LOGIC; 
  signal UFIX2FLT_N1799 : STD_LOGIC; 
  signal UFIX2FLT_N1801 : STD_LOGIC; 
  signal UFIX2FLT_N1256 : STD_LOGIC; 
  signal UFIX2FLT_N1257 : STD_LOGIC; 
  signal UFIX2FLT_C578_C14_C1_O : STD_LOGIC; 
  signal UFIX2FLT_N1803 : STD_LOGIC; 
  signal UFIX2FLT_N1805 : STD_LOGIC;