tb.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;

entity TB_FltAdder is
end TB_FltAdder;

architecture TBA_FltAdder of TB_FltAdder is

    component FLTADDER     
	port(CLK : in STD_LOGIC := 'X'; 
         DINB : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
         DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
         DINA : in STD_LOGIC_VECTOR ( 31 downto 0 ));
    end component;
    
    signal DInA    	: std_logic_vector(31 downto 0);   
    signal DInB    	: std_logic_vector(31 downto 0);
    signal DOut    	: std_logic_vector(31 downto 0);
    signal DOutRead	: std_logic_vector(31 downto 0);
    signal Clk   	: std_logic;
    
begin

    dut : FLTADDER
    port map(DInA => DInA,
	         DInB => DInB,
	         DOut => DOut,
	         Clk  => Clk );
	         
	process 
		file DA : text open read_mode is "DataB.dat"; 
		file DO : text open read_mode is "DataO.dat"; 
		variable DLine : line;
		variable OLine : line;
		variable DataA : integer;
		variable DataB : integer;
		variable Res   : integer;
	begin
		wait until Clk = '1' and Clk'event;
			readline(DA,DLine);
			read(DLine,DataA);
			read(DLine,DataB);
			DInA <= CONV_STD_LOGIC_VECTOR(DataA,32) after 5 ns;
			DInB <= CONV_STD_LOGIC_VECTOR(DataB,32) after 5 ns;
			readline(DO,OLine);
			read(OLine,Res);
			DOutRead <= CONV_STD_LOGIC_VECTOR(Res,32);
			if DOutRead /= DOut then
			    assert false report "Two values are not the same"
    			severity error; 
			end if;
	end process;		         

end TBA_FltAdder;