time_sim.vhd

台湾全华科技VHDL教材实例

      O => D3_4_INBLOCK_I
    );
  D3_4_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D3_4_INBLOCK_I,
      O => N_D3(4)
    );
  D3_5_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D3(5),
      O => D3_5_INBLOCK_I
    );
  D3_5_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D3_5_INBLOCK_I,
      O => N_D3(5)
    );
  D3_6_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D3(6),
      O => D3_6_INBLOCK_I
    );
  D3_6_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D3_6_INBLOCK_I,
      O => N_D3(6)
    );
  D3_7_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D3(7),
      O => D3_7_INBLOCK_I
    );
  D3_7_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D3_7_INBLOCK_I,
      O => N_D3(7)
    );
  D4_0_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D4(0),
      O => D4_0_INBLOCK_I
    );
  D4_0_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D4_0_INBLOCK_I,
      O => N_D4(0)
    );
  D4_1_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D4(1),
      O => D4_1_INBLOCK_I
    );
  D4_1_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D4_1_INBLOCK_I,
      O => N_D4(1)
    );
  D4_2_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D4(2),
      O => D4_2_INBLOCK_I
    );
  D4_2_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D4_2_INBLOCK_I,
      O => N_D4(2)
    );
  D4_3_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D4(3),
      O => D4_3_INBLOCK_I
    );
  D4_3_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D4_3_INBLOCK_I,
      O => N_D4(3)
    );
  D4_4_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D4(4),
      O => D4_4_INBLOCK_I
    );
  D4_4_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D4_4_INBLOCK_I,
      O => N_D4(4)
    );
  D4_5_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D4(5),
      O => D4_5_INBLOCK_I
    );
  D4_5_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D4_5_INBLOCK_I,
      O => N_D4(5)
    );
  D4_6_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D4(6),
      O => D4_6_INBLOCK_I
    );
  D4_6_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D4_6_INBLOCK_I,
      O => N_D4(6)
    );
  D4_7_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D4(7),
      O => D4_7_INBLOCK_I
    );
  D4_7_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D4_7_INBLOCK_I,
      O => N_D4(7)
    );
  Q_0_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N96,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_0_OUTBLOCK_OQ
    );
  Q_0_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_0_OUTBLOCK_OQ,
      O => Q(0),
      CTL => Q_0_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_1_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N97,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_1_OUTBLOCK_OQ
    );
  Q_1_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_1_OUTBLOCK_OQ,
      O => Q(1),
      CTL => Q_1_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_2_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N98,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_2_OUTBLOCK_OQ
    );
  Q_2_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_2_OUTBLOCK_OQ,
      O => Q(2),
      CTL => Q_2_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_3_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N99,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_3_OUTBLOCK_OQ
    );
  Q_3_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_3_OUTBLOCK_OQ,
      O => Q(3),
      CTL => Q_3_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_4_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N100,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_4_OUTBLOCK_OQ
    );
  Q_4_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_4_OUTBLOCK_OQ,
      O => Q(4),
      CTL => Q_4_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_5_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N101,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_5_OUTBLOCK_OQ
    );
  Q_5_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_5_OUTBLOCK_OQ,
      O => Q(5),
      CTL => Q_5_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_6_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N102,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_6_OUTBLOCK_OQ
    );
  Q_6_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_6_OUTBLOCK_OQ,
      O => Q(6),
      CTL => Q_6_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_7_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N103,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_7_OUTBLOCK_OQ
    );
  Q_7_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_7_OUTBLOCK_OQ,
      O => Q(7),
      CTL => Q_7_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_8_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N104,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_8_OUTBLOCK_OQ
    );
  Q_8_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_8_OUTBLOCK_OQ,
      O => Q(8),
      CTL => Q_8_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_9_OUTBLOCK_OUTFF : X_FF 
    port map (
      I => N105,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => Q_9_OUTBLOCK_OQ
    );
  Q_9_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI 
    port map (
      I => Q_9_OUTBLOCK_OQ,
      O => Q(9),
      CTL => Q_9_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_100 : X_INV 
    port map (
      I => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_101 : X_INV 
    port map (
      I => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_102 : X_INV 
    port map (
      I => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_103 : X_INV 
    port map (
      I => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_104 : X_INV 
    port map (
      I => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_105 : X_INV 
    port map (
      I => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_106 : X_INV 
    port map (
      I => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_107 : X_INV 
    port map (
      I => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  N96_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_108 : X_INV 
    port map (
      I => N96_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N96_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_109 : X_INV 
    port map (
      I => N97_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => N97_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_110 : X_INV 
    port map (
      I => N97_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N97_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_111 : X_INV 
    port map (
      I => N99_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => N99_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_112 : X_INV 
    port map (
      I => N99_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N99_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_113 : X_INV 
    port map (
      I => N101_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => N101_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_114 : X_INV 
    port map (
      I => N101_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N101_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_115 : X_INV 
    port map (
      I => N103_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => N103_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_116 : X_INV 
    port map (
      I => N103_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N103_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_117 : X_INV 
    port map (
      I => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_118 : X_INV 
    port map (
      I => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_119 : X_INV 
    port map (
      I => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_120 : X_INV 
    port map (
      I => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_121 : X_INV 
    port map (
      I => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_122 : X_INV 
    port map (
      I => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_123 : X_INV 
    port map (
      I => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV
    );
  SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV_124 : X_INV 
    port map (
      I => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV
    );
  Q_0_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_125 : X_INV 
    port map (
      I => GTS,
      O => Q_0_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_1_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_126 : X_INV 
    port map (
      I => GTS,
      O => Q_1_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_2_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_127 : X_INV 
    port map (
      I => GTS,
      O => Q_2_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_3_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_128 : X_INV 
    port map (
      I => GTS,
      O => Q_3_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_4_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_129 : X_INV 
    port map (
      I => GTS,
      O => Q_4_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_5_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_130 : X_INV 
    port map (
      I => GTS,
      O => Q_5_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_6_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_131 : X_INV 
    port map (
      I => GTS,
      O => Q_6_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_7_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_132 : X_INV 
    port map (
      I => GTS,
      O => Q_7_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_8_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_133 : X_INV 
    port map (
      I => GTS,
      O => Q_8_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  Q_9_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_134 : X_INV 
    port map (
      I => GTS,
      O => Q_9_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV
    );
  VCC_135 : X_ONE 
    port map (
      O => VCC
    );
  GND_136 : X_ZERO 
    port map (
      O => GND
    );
  ROC_NGD2VHDL : ROC port map (O => GSR);
  TOC_NGD2VHDL : TOC port map (O => GTS);
end STRUCTURE;