time_sim.vhd

台湾全华科技VHDL教材实例

      I => SUMA_3_DFF_OUT_QYDFF,
      O => SUMA(4)
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND2_79 : X_AND2 
    port map (
      I0 => C7_N11,
      I1 => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_80 : X_AND2 
    port map (
      I0 => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => N_D1(3),
      O => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => SUMA_3_FGBLOCK_COUT0
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C7_N18
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND4_81 : X_AND2 
    port map (
      I0 => SUMA_3_FGBLOCK_COUT0,
      I1 => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_82 : X_AND2 
    port map (
      I0 => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => N_D1(4),
      O => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3_83 : X_XOR2 
    port map (
      I0 => N_D2(4),
      I1 => N_D1(4),
      O => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1_84 : X_XOR2 
    port map (
      I0 => N_D1(3),
      I1 => N_D2(3),
      O => SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  SUMA_3_FGBLOCK_LUTRAM_FLUT_XOR0_85 : X_XOR2 
    port map (
      I0 => N_D1(3),
      I1 => N_D2(3),
      O => SUMA_3_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  SUMA_3_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMA_3_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C7_N11,
      O => SUMA_3_F
    );
  SUMA_3_FGBLOCK_LUTRAM_GLUT_XOR0_86 : X_XOR2 
    port map (
      I0 => N_D2(4),
      I1 => SUMA_3_FGBLOCK_COUT0,
      O => SUMA_3_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  SUMA_3_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMA_3_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => N_D1(4),
      O => SUMA_3_G
    );
  SUMA_5_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMA_5_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_5_DFF_OUT_QYDFF
    );
  SUMA_5_DFF_OUT_DFFX : X_FF 
    port map (
      I => SUMA_5_F,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_5_DFF_OUT_QXDFF
    );
  SUMA_5_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => SUMA_5_DFF_OUT_QXDFF,
      O => SUMA(5)
    );
  SUMA_5_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMA_5_DFF_OUT_QYDFF,
      O => SUMA(6)
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND2_87 : X_AND2 
    port map (
      I0 => C7_N18,
      I1 => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_88 : X_AND2 
    port map (
      I0 => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => N_D1(5),
      O => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => SUMA_5_FGBLOCK_COUT0
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C7_N25
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND4_89 : X_AND2 
    port map (
      I0 => SUMA_5_FGBLOCK_COUT0,
      I1 => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_90 : X_AND2 
    port map (
      I0 => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => N_D1(6),
      O => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3_91 : X_XOR2 
    port map (
      I0 => N_D2(6),
      I1 => N_D1(6),
      O => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1_92 : X_XOR2 
    port map (
      I0 => N_D1(5),
      I1 => N_D2(5),
      O => SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  SUMA_5_FGBLOCK_LUTRAM_FLUT_XOR0_93 : X_XOR2 
    port map (
      I0 => N_D1(5),
      I1 => N_D2(5),
      O => SUMA_5_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  SUMA_5_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMA_5_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C7_N18,
      O => SUMA_5_F
    );
  SUMA_5_FGBLOCK_LUTRAM_GLUT_XOR0_94 : X_XOR2 
    port map (
      I0 => N_D2(6),
      I1 => SUMA_5_FGBLOCK_COUT0,
      O => SUMA_5_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  SUMA_5_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMA_5_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => N_D1(6),
      O => SUMA_5_G
    );
  SUMA_7_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMA_7_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_7_DFF_OUT_QYDFF
    );
  SUMA_7_DFF_OUT_DFFX : X_FF 
    port map (
      I => SUMA_7_F,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_7_DFF_OUT_QXDFF
    );
  SUMA_7_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => SUMA_7_DFF_OUT_QXDFF,
      O => SUMA(7)
    );
  SUMA_7_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMA_7_DFF_OUT_QYDFF,
      O => SUMA(8)
    );
  SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND2_95 : X_AND2 
    port map (
      I0 => C7_N25,
      I1 => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_96 : X_AND2 
    port map (
      I0 => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => N_D1(7),
      O => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => SUMA_7_COUT
    );
  SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1_97 : X_XOR2 
    port map (
      I0 => N_D1(7),
      I1 => N_D2(7),
      O => SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  SUMA_7_FGBLOCK_LUTRAM_FLUT_XOR0_98 : X_XOR2 
    port map (
      I0 => N_D1(7),
      I1 => N_D2(7),
      O => SUMA_7_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  SUMA_7_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMA_7_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C7_N25,
      O => SUMA_7_F
    );
  SUMA_7_FGBLOCK_LUTRAM_GLUT_XOR0_99 : X_XOR2 
    port map (
      I0 => N_D2(7),
      I1 => SUMA_7_COUT,
      O => SUMA_7_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  SUMA_7_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMA_7_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => N_D1(7),
      O => SUMA_7_G
    );
  CLK_CLKINMUX : X_BUF 
    port map (
      I => CLK,
      O => CLK_INT
    );
  D1_0_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D1(0),
      O => D1_0_INBLOCK_I
    );
  D1_0_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D1_0_INBLOCK_I,
      O => N_D1(0)
    );
  D1_1_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D1(1),
      O => D1_1_INBLOCK_I
    );
  D1_1_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D1_1_INBLOCK_I,
      O => N_D1(1)
    );
  D1_2_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D1(2),
      O => D1_2_INBLOCK_I
    );
  D1_2_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D1_2_INBLOCK_I,
      O => N_D1(2)
    );
  D1_3_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D1(3),
      O => D1_3_INBLOCK_I
    );
  D1_3_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D1_3_INBLOCK_I,
      O => N_D1(3)
    );
  D1_4_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D1(4),
      O => D1_4_INBLOCK_I
    );
  D1_4_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D1_4_INBLOCK_I,
      O => N_D1(4)
    );
  D1_5_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D1(5),
      O => D1_5_INBLOCK_I
    );
  D1_5_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D1_5_INBLOCK_I,
      O => N_D1(5)
    );
  D1_6_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D1(6),
      O => D1_6_INBLOCK_I
    );
  D1_6_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D1_6_INBLOCK_I,
      O => N_D1(6)
    );
  D1_7_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D1(7),
      O => D1_7_INBLOCK_I
    );
  D1_7_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D1_7_INBLOCK_I,
      O => N_D1(7)
    );
  D2_0_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D2(0),
      O => D2_0_INBLOCK_I
    );
  D2_0_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D2_0_INBLOCK_I,
      O => N_D2(0)
    );
  D2_1_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D2(1),
      O => D2_1_INBLOCK_I
    );
  D2_1_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D2_1_INBLOCK_I,
      O => N_D2(1)
    );
  D2_2_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D2(2),
      O => D2_2_INBLOCK_I
    );
  D2_2_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D2_2_INBLOCK_I,
      O => N_D2(2)
    );
  D2_3_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D2(3),
      O => D2_3_INBLOCK_I
    );
  D2_3_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D2_3_INBLOCK_I,
      O => N_D2(3)
    );
  D2_4_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D2(4),
      O => D2_4_INBLOCK_I
    );
  D2_4_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D2_4_INBLOCK_I,
      O => N_D2(4)
    );
  D2_5_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D2(5),
      O => D2_5_INBLOCK_I
    );
  D2_5_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D2_5_INBLOCK_I,
      O => N_D2(5)
    );
  D2_6_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D2(6),
      O => D2_6_INBLOCK_I
    );
  D2_6_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D2_6_INBLOCK_I,
      O => N_D2(6)
    );
  D2_7_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D2(7),
      O => D2_7_INBLOCK_I
    );
  D2_7_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D2_7_INBLOCK_I,
      O => N_D2(7)
    );
  D3_0_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D3(0),
      O => D3_0_INBLOCK_I
    );
  D3_0_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D3_0_INBLOCK_I,
      O => N_D3(0)
    );
  D3_1_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D3(1),
      O => D3_1_INBLOCK_I
    );
  D3_1_INBLOCK_I2MUX : X_BUF 
    port map (
      I => D3_1_INBLOCK_I,
      O => N_D3(1)
    );
  D3_2_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D3(2),
      O => D3_2_INBLOCK_I
    );
  D3_2_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D3_2_INBLOCK_I,
      O => N_D3(2)
    );
  D3_3_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D3(3),
      O => D3_3_INBLOCK_I
    );
  D3_3_INBLOCK_I1MUX : X_BUF 
    port map (
      I => D3_3_INBLOCK_I,
      O => N_D3(3)
    );
  D3_4_INBLOCK_IN_BUF : X_BUF 
    port map (
      I => D3(4),