time_sim.vhd

台湾全华科技VHDL教材实例

    port map (
      I0 => SUMB(2),
      I1 => SUMA(2),
      O => N97_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_XOR1_41 : X_XOR2 
    port map (
      I0 => SUMA(1),
      I1 => SUMB(1),
      O => N97_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  N97_FGBLOCK_LUTRAM_FLUT_XOR0_42 : X_XOR2 
    port map (
      I0 => SUMA(1),
      I1 => SUMB(1),
      O => N97_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  N97_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => N97_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C6_N4,
      O => N97_F
    );
  N97_FGBLOCK_LUTRAM_GLUT_XOR0_43 : X_XOR2 
    port map (
      I0 => SUMB(2),
      I1 => N97_FGBLOCK_COUT0,
      O => N97_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  N97_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => N97_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => SUMA(2),
      O => N97_G
    );
  N99_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N99_G,
      O => N100
    );
  N99_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N99_F,
      O => N99
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_AND2_44 : X_AND2 
    port map (
      I0 => C6_N11,
      I1 => N99_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => N99_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_AND3_45 : X_AND2 
    port map (
      I0 => N99_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => SUMA(3),
      O => N99_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => N99_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => N99_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => N99_FGBLOCK_COUT0
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => N99_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => N99_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C6_N18
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_AND4_46 : X_AND2 
    port map (
      I0 => N99_FGBLOCK_COUT0,
      I1 => N99_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N99_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_AND5_47 : X_AND2 
    port map (
      I0 => N99_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => SUMA(4),
      O => N99_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_XOR3_48 : X_XOR2 
    port map (
      I0 => SUMB(4),
      I1 => SUMA(4),
      O => N99_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  N99_FGBLOCK_LUTRAM_CARRYBLK_XOR1_49 : X_XOR2 
    port map (
      I0 => SUMA(3),
      I1 => SUMB(3),
      O => N99_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  N99_FGBLOCK_LUTRAM_FLUT_XOR0_50 : X_XOR2 
    port map (
      I0 => SUMA(3),
      I1 => SUMB(3),
      O => N99_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  N99_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => N99_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C6_N11,
      O => N99_F
    );
  N99_FGBLOCK_LUTRAM_GLUT_XOR0_51 : X_XOR2 
    port map (
      I0 => SUMB(4),
      I1 => N99_FGBLOCK_COUT0,
      O => N99_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  N99_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => N99_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => SUMA(4),
      O => N99_G
    );
  N101_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N101_G,
      O => N102
    );
  N101_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N101_F,
      O => N101
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_AND2_52 : X_AND2 
    port map (
      I0 => C6_N18,
      I1 => N101_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => N101_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_AND3_53 : X_AND2 
    port map (
      I0 => N101_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => SUMA(5),
      O => N101_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => N101_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => N101_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => N101_FGBLOCK_COUT0
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => N101_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => N101_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C6_N25
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_AND4_54 : X_AND2 
    port map (
      I0 => N101_FGBLOCK_COUT0,
      I1 => N101_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N101_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_AND5_55 : X_AND2 
    port map (
      I0 => N101_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => SUMA(6),
      O => N101_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_XOR3_56 : X_XOR2 
    port map (
      I0 => SUMB(6),
      I1 => SUMA(6),
      O => N101_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  N101_FGBLOCK_LUTRAM_CARRYBLK_XOR1_57 : X_XOR2 
    port map (
      I0 => SUMA(5),
      I1 => SUMB(5),
      O => N101_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  N101_FGBLOCK_LUTRAM_FLUT_XOR0_58 : X_XOR2 
    port map (
      I0 => SUMA(5),
      I1 => SUMB(5),
      O => N101_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  N101_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => N101_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C6_N18,
      O => N101_F
    );
  N101_FGBLOCK_LUTRAM_GLUT_XOR0_59 : X_XOR2 
    port map (
      I0 => SUMB(6),
      I1 => N101_FGBLOCK_COUT0,
      O => N101_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  N101_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => N101_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => SUMA(6),
      O => N101_G
    );
  N103_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N103_G,
      O => N104
    );
  N103_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N103_F,
      O => N103
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_AND2_60 : X_AND2 
    port map (
      I0 => C6_N25,
      I1 => N103_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => N103_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_AND3_61 : X_AND2 
    port map (
      I0 => N103_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => SUMA(7),
      O => N103_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => N103_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => N103_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => N103_FGBLOCK_COUT0
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => N103_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => N103_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C6_N32
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_AND4_62 : X_AND2 
    port map (
      I0 => N103_FGBLOCK_COUT0,
      I1 => N103_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N103_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_AND5_63 : X_AND2 
    port map (
      I0 => N103_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => SUMA(8),
      O => N103_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_XOR3_64 : X_XOR2 
    port map (
      I0 => SUMB(8),
      I1 => SUMA(8),
      O => N103_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  N103_FGBLOCK_LUTRAM_CARRYBLK_XOR1_65 : X_XOR2 
    port map (
      I0 => SUMA(7),
      I1 => SUMB(7),
      O => N103_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  N103_FGBLOCK_LUTRAM_FLUT_XOR0_66 : X_XOR2 
    port map (
      I0 => SUMA(7),
      I1 => SUMB(7),
      O => N103_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  N103_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => N103_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C6_N25,
      O => N103_F
    );
  N103_FGBLOCK_LUTRAM_GLUT_XOR0_67 : X_XOR2 
    port map (
      I0 => SUMB(8),
      I1 => N103_FGBLOCK_COUT0,
      O => N103_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  N103_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => N103_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => SUMA(8),
      O => N103_G
    );
  SUMA_0_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMA_0_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_0_DFF_OUT_QYDFF
    );
  SUMA_0_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMA_0_DFF_OUT_QYDFF,
      O => SUMA(0)
    );
  SUMA_0_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SUMA_0_F,
      O => GLOBAL_LOGIC0_1
    );
  SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C7_N4
    );
  SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND4_68 : X_AND2 
    port map (
      I0 => GLOBAL_LOGIC0_1,
      I1 => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_69 : X_AND2 
    port map (
      I0 => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => N_D1(0),
      O => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3_70 : X_XOR2 
    port map (
      I0 => N_D2(0),
      I1 => N_D1(0),
      O => SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  SUMA_0_FGBLOCK_LUTRAM_FLUT_ZERO0 : X_ZERO 
    port map (
      O => SUMA_0_F
    );
  SUMA_0_FGBLOCK_LUTRAM_GLUT_XOR0 : X_XOR2 
    port map (
      I0 => N_D2(0),
      I1 => N_D1(0),
      O => SUMA_0_G
    );
  SUMA_1_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMA_1_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_1_DFF_OUT_QYDFF
    );
  SUMA_1_DFF_OUT_DFFX : X_FF 
    port map (
      I => SUMA_1_F,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_1_DFF_OUT_QXDFF
    );
  SUMA_1_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => SUMA_1_DFF_OUT_QXDFF,
      O => SUMA(1)
    );
  SUMA_1_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMA_1_DFF_OUT_QYDFF,
      O => SUMA(2)
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND2_71 : X_AND2 
    port map (
      I0 => C7_N4,
      I1 => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_72 : X_AND2 
    port map (
      I0 => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => N_D1(1),
      O => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => SUMA_1_FGBLOCK_COUT0
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C7_N11
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND4_73 : X_AND2 
    port map (
      I0 => SUMA_1_FGBLOCK_COUT0,
      I1 => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_74 : X_AND2 
    port map (
      I0 => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => N_D1(2),
      O => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3_75 : X_XOR2 
    port map (
      I0 => N_D2(2),
      I1 => N_D1(2),
      O => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1_76 : X_XOR2 
    port map (
      I0 => N_D1(1),
      I1 => N_D2(1),
      O => SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  SUMA_1_FGBLOCK_LUTRAM_FLUT_XOR0_77 : X_XOR2 
    port map (
      I0 => N_D1(1),
      I1 => N_D2(1),
      O => SUMA_1_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  SUMA_1_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMA_1_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C7_N4,
      O => SUMA_1_F
    );
  SUMA_1_FGBLOCK_LUTRAM_GLUT_XOR0_78 : X_XOR2 
    port map (
      I0 => N_D2(2),
      I1 => SUMA_1_FGBLOCK_COUT0,
      O => SUMA_1_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  SUMA_1_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMA_1_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => N_D1(2),
      O => SUMA_1_G
    );
  SUMA_3_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMA_3_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_3_DFF_OUT_QYDFF
    );
  SUMA_3_DFF_OUT_DFFX : X_FF 
    port map (
      I => SUMA_3_F,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMA_3_DFF_OUT_QXDFF
    );
  SUMA_3_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => SUMA_3_DFF_OUT_QXDFF,
      O => SUMA(3)
    );
  SUMA_3_DFF_OUT_YQMUX : X_BUF 
    port map (