time_sim.vhd

台湾全华科技VHDL教材实例

    );
  SUMB_1_DFF_OUT_DFFX : X_FF 
    port map (
      I => SUMB_1_F,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_1_DFF_OUT_QXDFF
    );
  SUMB_1_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => SUMB_1_DFF_OUT_QXDFF,
      O => SUMB(1)
    );
  SUMB_1_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMB_1_DFF_OUT_QYDFF,
      O => SUMB(2)
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND2_4 : X_AND2 
    port map (
      I0 => C5_N4,
      I1 => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_5 : X_AND2 
    port map (
      I0 => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => N_D3(1),
      O => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => SUMB_1_FGBLOCK_COUT0
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C5_N11
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND4_6 : X_AND2 
    port map (
      I0 => SUMB_1_FGBLOCK_COUT0,
      I1 => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_7 : X_AND2 
    port map (
      I0 => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => N_D3(2),
      O => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3_8 : X_XOR2 
    port map (
      I0 => N_D4(2),
      I1 => N_D3(2),
      O => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1_9 : X_XOR2 
    port map (
      I0 => N_D3(1),
      I1 => N_D4(1),
      O => SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  SUMB_1_FGBLOCK_LUTRAM_FLUT_XOR0_10 : X_XOR2 
    port map (
      I0 => N_D3(1),
      I1 => N_D4(1),
      O => SUMB_1_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  SUMB_1_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMB_1_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C5_N4,
      O => SUMB_1_F
    );
  SUMB_1_FGBLOCK_LUTRAM_GLUT_XOR0_11 : X_XOR2 
    port map (
      I0 => N_D4(2),
      I1 => SUMB_1_FGBLOCK_COUT0,
      O => SUMB_1_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  SUMB_1_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMB_1_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => N_D3(2),
      O => SUMB_1_G
    );
  SUMB_3_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMB_3_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_3_DFF_OUT_QYDFF
    );
  SUMB_3_DFF_OUT_DFFX : X_FF 
    port map (
      I => SUMB_3_F,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_3_DFF_OUT_QXDFF
    );
  SUMB_3_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => SUMB_3_DFF_OUT_QXDFF,
      O => SUMB(3)
    );
  SUMB_3_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMB_3_DFF_OUT_QYDFF,
      O => SUMB(4)
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND2_12 : X_AND2 
    port map (
      I0 => C5_N11,
      I1 => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_13 : X_AND2 
    port map (
      I0 => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => N_D3(3),
      O => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => SUMB_3_FGBLOCK_COUT0
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C5_N18
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND4_14 : X_AND2 
    port map (
      I0 => SUMB_3_FGBLOCK_COUT0,
      I1 => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_15 : X_AND2 
    port map (
      I0 => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => N_D3(4),
      O => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3_16 : X_XOR2 
    port map (
      I0 => N_D4(4),
      I1 => N_D3(4),
      O => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1_17 : X_XOR2 
    port map (
      I0 => N_D3(3),
      I1 => N_D4(3),
      O => SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  SUMB_3_FGBLOCK_LUTRAM_FLUT_XOR0_18 : X_XOR2 
    port map (
      I0 => N_D3(3),
      I1 => N_D4(3),
      O => SUMB_3_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  SUMB_3_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMB_3_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C5_N11,
      O => SUMB_3_F
    );
  SUMB_3_FGBLOCK_LUTRAM_GLUT_XOR0_19 : X_XOR2 
    port map (
      I0 => N_D4(4),
      I1 => SUMB_3_FGBLOCK_COUT0,
      O => SUMB_3_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  SUMB_3_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMB_3_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => N_D3(4),
      O => SUMB_3_G
    );
  SUMB_5_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMB_5_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_5_DFF_OUT_QYDFF
    );
  SUMB_5_DFF_OUT_DFFX : X_FF 
    port map (
      I => SUMB_5_F,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_5_DFF_OUT_QXDFF
    );
  SUMB_5_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => SUMB_5_DFF_OUT_QXDFF,
      O => SUMB(5)
    );
  SUMB_5_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMB_5_DFF_OUT_QYDFF,
      O => SUMB(6)
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND2_20 : X_AND2 
    port map (
      I0 => C5_N18,
      I1 => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_21 : X_AND2 
    port map (
      I0 => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => N_D3(5),
      O => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => SUMB_5_FGBLOCK_COUT0
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C5_N25
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND4_22 : X_AND2 
    port map (
      I0 => SUMB_5_FGBLOCK_COUT0,
      I1 => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_23 : X_AND2 
    port map (
      I0 => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => N_D3(6),
      O => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3_24 : X_XOR2 
    port map (
      I0 => N_D4(6),
      I1 => N_D3(6),
      O => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1_25 : X_XOR2 
    port map (
      I0 => N_D3(5),
      I1 => N_D4(5),
      O => SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  SUMB_5_FGBLOCK_LUTRAM_FLUT_XOR0_26 : X_XOR2 
    port map (
      I0 => N_D3(5),
      I1 => N_D4(5),
      O => SUMB_5_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  SUMB_5_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMB_5_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C5_N18,
      O => SUMB_5_F
    );
  SUMB_5_FGBLOCK_LUTRAM_GLUT_XOR0_27 : X_XOR2 
    port map (
      I0 => N_D4(6),
      I1 => SUMB_5_FGBLOCK_COUT0,
      O => SUMB_5_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  SUMB_5_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMB_5_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => N_D3(6),
      O => SUMB_5_G
    );
  SUMB_7_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMB_7_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_7_DFF_OUT_QYDFF
    );
  SUMB_7_DFF_OUT_DFFX : X_FF 
    port map (
      I => SUMB_7_F,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_7_DFF_OUT_QXDFF
    );
  SUMB_7_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => SUMB_7_DFF_OUT_QXDFF,
      O => SUMB(7)
    );
  SUMB_7_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMB_7_DFF_OUT_QYDFF,
      O => SUMB(8)
    );
  SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND2_28 : X_AND2 
    port map (
      I0 => C5_N25,
      I1 => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_29 : X_AND2 
    port map (
      I0 => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => N_D3(7),
      O => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => SUMB_7_COUT
    );
  SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1_30 : X_XOR2 
    port map (
      I0 => N_D3(7),
      I1 => N_D4(7),
      O => SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1
    );
  SUMB_7_FGBLOCK_LUTRAM_FLUT_XOR0_31 : X_XOR2 
    port map (
      I0 => N_D3(7),
      I1 => N_D4(7),
      O => SUMB_7_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  SUMB_7_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMB_7_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C5_N25,
      O => SUMB_7_F
    );
  SUMB_7_FGBLOCK_LUTRAM_GLUT_XOR0_32 : X_XOR2 
    port map (
      I0 => N_D4(7),
      I1 => SUMB_7_COUT,
      O => SUMB_7_FGBLOCK_LUTRAM_GLUT_XOR0
    );
  SUMB_7_FGBLOCK_LUTRAM_GLUT_XOR1 : X_XOR2 
    port map (
      I0 => SUMB_7_FGBLOCK_LUTRAM_GLUT_XOR0,
      I1 => N_D3(7),
      O => SUMB_7_G
    );
  N96_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N96_G,
      O => N96
    );
  N96_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N96_F,
      O => GLOBAL_LOGIC0_0
    );
  N96_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => N96_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => N96_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C6_N4
    );
  N96_FGBLOCK_LUTRAM_CARRYBLK_AND4_33 : X_AND2 
    port map (
      I0 => GLOBAL_LOGIC0_0,
      I1 => N96_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N96_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  N96_FGBLOCK_LUTRAM_CARRYBLK_AND5_34 : X_AND2 
    port map (
      I0 => N96_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => SUMA(0),
      O => N96_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  N96_FGBLOCK_LUTRAM_CARRYBLK_XOR3_35 : X_XOR2 
    port map (
      I0 => SUMB(0),
      I1 => SUMA(0),
      O => N96_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  N96_FGBLOCK_LUTRAM_FLUT_ZERO0 : X_ZERO 
    port map (
      O => N96_F
    );
  N96_FGBLOCK_LUTRAM_GLUT_XOR0 : X_XOR2 
    port map (
      I0 => SUMB(0),
      I1 => SUMA(0),
      O => N96_G
    );
  N97_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N97_G,
      O => N98
    );
  N97_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N97_F,
      O => N97
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_AND2_36 : X_AND2 
    port map (
      I0 => C6_N4,
      I1 => N97_FGBLOCK_LUTRAM_CARRYBLK_XOR1,
      O => N97_FGBLOCK_LUTRAM_CARRYBLK_AND2
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_AND3_37 : X_AND2 
    port map (
      I0 => N97_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV,
      I1 => SUMA(1),
      O => N97_FGBLOCK_LUTRAM_CARRYBLK_AND3
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_OR0 : X_OR2 
    port map (
      I0 => N97_FGBLOCK_LUTRAM_CARRYBLK_AND2,
      I1 => N97_FGBLOCK_LUTRAM_CARRYBLK_AND3,
      O => N97_FGBLOCK_COUT0
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => N97_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => N97_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C6_N11
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_AND4_38 : X_AND2 
    port map (
      I0 => N97_FGBLOCK_COUT0,
      I1 => N97_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => N97_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_AND5_39 : X_AND2 
    port map (
      I0 => N97_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => SUMA(2),
      O => N97_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  N97_FGBLOCK_LUTRAM_CARRYBLK_XOR3_40 : X_XOR2