time_sim.vhd

台湾全华科技VHDL教材实例

-- Xilinx Vhdl produced by program ngd2vhdl C.16
-- Command: -w Add4In.nga time_sim.vhd 
-- Options: -w -ti UUT 
-- Date: Thu Jun 01 13:18:57 2000 
-- Input file: Add4In.nga
-- Output file: time_sim.vhd
-- Tmp file: C:/WINDOWS/TEMP/xil_6
-- Design name: Add4In
-- Xilinx: C:/Fndtn
-- # of Entities: 1
-- Device: 4002xlpc84-09

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity ADD4IN is 
  port (
    CLK : in STD_LOGIC := 'X'; 
    D1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    D2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    D3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    D4 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    Q : out STD_LOGIC_VECTOR ( 9 downto 0 ) 
  );
end ADD4IN;

architecture STRUCTURE of ADD4IN is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal C5_N4 : STD_LOGIC; 
  signal C5_N11 : STD_LOGIC; 
  signal C5_N18 : STD_LOGIC; 
  signal C5_N25 : STD_LOGIC; 
  signal N96 : STD_LOGIC; 
  signal C6_N4 : STD_LOGIC; 
  signal N97 : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal C6_N11 : STD_LOGIC; 
  signal N99 : STD_LOGIC; 
  signal N100 : STD_LOGIC; 
  signal C6_N18 : STD_LOGIC; 
  signal N101 : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal C6_N25 : STD_LOGIC; 
  signal N103 : STD_LOGIC; 
  signal N104 : STD_LOGIC; 
  signal C6_N32 : STD_LOGIC; 
  signal N105 : STD_LOGIC; 
  signal C7_N4 : STD_LOGIC; 
  signal C7_N11 : STD_LOGIC; 
  signal C7_N18 : STD_LOGIC; 
  signal C7_N25 : STD_LOGIC; 
  signal CLK_BUFGED : STD_LOGIC; 
  signal CLK_INT : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_1 : STD_LOGIC; 
  signal N105_F : STD_LOGIC; 
  signal N105_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMB_0_F : STD_LOGIC; 
  signal SUMB_0_G : STD_LOGIC; 
  signal SUMB_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal SUMB_1_F : STD_LOGIC; 
  signal SUMB_1_G : STD_LOGIC; 
  signal SUMB_1_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMB_1_DFF_OUT_QXDFF : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_COUT0 : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal SUMB_3_F : STD_LOGIC; 
  signal SUMB_3_G : STD_LOGIC; 
  signal SUMB_3_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMB_3_DFF_OUT_QXDFF : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_COUT0 : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal SUMB_5_F : STD_LOGIC; 
  signal SUMB_5_G : STD_LOGIC; 
  signal SUMB_5_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMB_5_DFF_OUT_QXDFF : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_COUT0 : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal SUMB_7_COUT : STD_LOGIC; 
  signal SUMB_7_F : STD_LOGIC; 
  signal SUMB_7_G : STD_LOGIC; 
  signal SUMB_7_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMB_7_DFF_OUT_QXDFF : STD_LOGIC; 
  signal SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal SUMB_7_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMB_7_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal N96_F : STD_LOGIC; 
  signal N96_G : STD_LOGIC; 
  signal N96_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal N96_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal N96_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal N97_F : STD_LOGIC; 
  signal N97_G : STD_LOGIC; 
  signal N97_FGBLOCK_COUT0 : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal N99_F : STD_LOGIC; 
  signal N99_G : STD_LOGIC; 
  signal N99_FGBLOCK_COUT0 : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal N101_F : STD_LOGIC; 
  signal N101_G : STD_LOGIC; 
  signal N101_FGBLOCK_COUT0 : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal N103_F : STD_LOGIC; 
  signal N103_G : STD_LOGIC; 
  signal N103_FGBLOCK_COUT0 : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal SUMA_0_F : STD_LOGIC; 
  signal SUMA_0_G : STD_LOGIC; 
  signal SUMA_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal SUMA_1_F : STD_LOGIC; 
  signal SUMA_1_G : STD_LOGIC; 
  signal SUMA_1_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMA_1_DFF_OUT_QXDFF : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_COUT0 : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal SUMA_3_F : STD_LOGIC; 
  signal SUMA_3_G : STD_LOGIC; 
  signal SUMA_3_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMA_3_DFF_OUT_QXDFF : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_COUT0 : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal SUMA_5_F : STD_LOGIC; 
  signal SUMA_5_G : STD_LOGIC; 
  signal SUMA_5_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMA_5_DFF_OUT_QXDFF : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_COUT0 : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR3 : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND4 : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND5 : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal SUMA_7_COUT : STD_LOGIC; 
  signal SUMA_7_F : STD_LOGIC; 
  signal SUMA_7_G : STD_LOGIC; 
  signal SUMA_7_DFF_OUT_QYDFF : STD_LOGIC; 
  signal SUMA_7_DFF_OUT_QXDFF : STD_LOGIC; 
  signal SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_XOR1 : STD_LOGIC; 
  signal SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND2 : STD_LOGIC; 
  signal SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND3 : STD_LOGIC; 
  signal SUMA_7_FGBLOCK_LUTRAM_FLUT_XOR0 : STD_LOGIC; 
  signal SUMA_7_FGBLOCK_LUTRAM_GLUT_XOR0 : STD_LOGIC; 
  signal D1_0_INBLOCK_I : STD_LOGIC; 
  signal D1_1_INBLOCK_I : STD_LOGIC; 
  signal D1_2_INBLOCK_I : STD_LOGIC; 
  signal D1_3_INBLOCK_I : STD_LOGIC; 
  signal D1_4_INBLOCK_I : STD_LOGIC; 
  signal D1_5_INBLOCK_I : STD_LOGIC; 
  signal D1_6_INBLOCK_I : STD_LOGIC; 
  signal D1_7_INBLOCK_I : STD_LOGIC; 
  signal D2_0_INBLOCK_I : STD_LOGIC; 
  signal D2_1_INBLOCK_I : STD_LOGIC; 
  signal D2_2_INBLOCK_I : STD_LOGIC; 
  signal D2_3_INBLOCK_I : STD_LOGIC; 
  signal D2_4_INBLOCK_I : STD_LOGIC; 
  signal D2_5_INBLOCK_I : STD_LOGIC; 
  signal D2_6_INBLOCK_I : STD_LOGIC; 
  signal D2_7_INBLOCK_I : STD_LOGIC; 
  signal D3_0_INBLOCK_I : STD_LOGIC; 
  signal D3_1_INBLOCK_I : STD_LOGIC; 
  signal D3_2_INBLOCK_I : STD_LOGIC; 
  signal D3_3_INBLOCK_I : STD_LOGIC; 
  signal D3_4_INBLOCK_I : STD_LOGIC; 
  signal D3_5_INBLOCK_I : STD_LOGIC; 
  signal D3_6_INBLOCK_I : STD_LOGIC; 
  signal D3_7_INBLOCK_I : STD_LOGIC; 
  signal D4_0_INBLOCK_I : STD_LOGIC; 
  signal D4_1_INBLOCK_I : STD_LOGIC; 
  signal D4_2_INBLOCK_I : STD_LOGIC; 
  signal D4_3_INBLOCK_I : STD_LOGIC; 
  signal D4_4_INBLOCK_I : STD_LOGIC; 
  signal D4_5_INBLOCK_I : STD_LOGIC; 
  signal D4_6_INBLOCK_I : STD_LOGIC; 
  signal D4_7_INBLOCK_I : STD_LOGIC; 
  signal Q_0_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_1_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_2_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_3_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_4_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_5_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_6_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_7_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_8_OUTBLOCK_OQ : STD_LOGIC; 
  signal Q_9_OUTBLOCK_OQ : STD_LOGIC; 
  signal SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal SUMB_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal SUMB_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal SUMB_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMB_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal N96_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal N97_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal N99_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal N101_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal N103_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMA_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal SUMA_1_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal SUMA_3_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal SUMA_5_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV : STD_LOGIC; 
  signal SUMA_7_FGBLOCK_LUTRAM_CARRYBLK_AND3_0_INV : STD_LOGIC; 
  signal Q_0_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_1_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_2_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_3_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_4_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_5_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_6_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_7_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_8_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal Q_9_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal N_D4 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal N_D3 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal SUMB : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal SUMA : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal N_D2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal N_D1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  C131 : X_CKBUF 
    port map (
      I => CLK_INT,
      O => CLK_BUFGED
    );
  N105_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N105_F,
      O => N105
    );
  N105_FGBLOCK_LUTRAM_FLUT_XOR0_0 : X_XOR2 
    port map (
      I0 => SUMA(8),
      I1 => SUMB(8),
      O => N105_FGBLOCK_LUTRAM_FLUT_XOR0
    );
  N105_FGBLOCK_LUTRAM_FLUT_XOR1 : X_XOR2 
    port map (
      I0 => N105_FGBLOCK_LUTRAM_FLUT_XOR0,
      I1 => C6_N32,
      O => N105_F
    );
  SUMB_0_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMB_0_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_0_DFF_OUT_QYDFF
    );
  SUMB_0_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => SUMB_0_DFF_OUT_QYDFF,
      O => SUMB(0)
    );
  SUMB_0_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SUMB_0_F,
      O => GLOBAL_LOGIC0
    );
  SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
    port map (
      I0 => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND4,
      I1 => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND5,
      O => C5_N4
    );
  SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND4_1 : X_AND2 
    port map (
      I0 => GLOBAL_LOGIC0,
      I1 => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3,
      O => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND4
    );
  SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_2 : X_AND2 
    port map (
      I0 => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV,
      I1 => N_D3(0),
      O => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_AND5
    );
  SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3_3 : X_XOR2 
    port map (
      I0 => N_D4(0),
      I1 => N_D3(0),
      O => SUMB_0_FGBLOCK_LUTRAM_CARRYBLK_XOR3
    );
  SUMB_0_FGBLOCK_LUTRAM_FLUT_ZERO0 : X_ZERO 
    port map (
      O => SUMB_0_F
    );
  SUMB_0_FGBLOCK_LUTRAM_GLUT_XOR0 : X_XOR2 
    port map (
      I0 => N_D4(0),
      I1 => N_D3(0),
      O => SUMB_0_G
    );
  SUMB_1_DFF_OUT_DFFY : X_FF 
    port map (
      I => SUMB_1_G,
      CLK => CLK_BUFGED,
      CE => VCC,
      SET => GND,
      RST => GSR,
      O => SUMB_1_DFF_OUT_QYDFF