v2_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.std_ulogic;

entity e is
 port(d 	: in std_logic;
      clk 	: in std_logic; 
      rst 	: in std_logic;
      oe 	: in std_logic;
      q 	: out std_logic);
end e;

architecture a of e is

	signal q_int : std_logic;

begin

	process(rst,clk)
	begin
		if rst = '0' then	
			q_int <= '0';
		elsif clk = '1' and clk'event then
			q_int <= d;
		end if;
	end process;
	
	q <= q_int when oe = '0' else
        'Z';
        
end a;