v2_3.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity porttest is
  port(InA	: in std_logic_vector(3 downto 0);
	   InB	: in std_logic;
	   OutA : out std_logic_vector(3 downto 0));
end porttest;

architecture A of porttest is

	signal OutATemp : std_logic_vector(3 downto 0);

begin
	OutATemp <= OutATemp + 1 when InB = '0' else
                InA;
	OutA <= OutATemp;
end A;