v2_0.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity E is
port(D    : in std_logic;
     Clk  : in std_logic; 
     Rst  : in std_logic;
     OE   : in std_logic;
     Q    : out std_logic);
end E;

architecture A of E is

	signal q_int : std_logic;
	
begin

	process(Rst,Clk)
	begin
		if Rst = '0' then	
			q_int <= '0';
		elsif clk = '1' and clk'event then
			q_int <= d;
		end if;
	end process;
	
	Q <= q_int when OE = '0' else
        'Z';
        
end A;