v2_4.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 8 行

library ieee;
use ieee.std_logic_1164.all;

package Define is
    type   StateF is (Idle, ABCDump, TLMDump, BusChk,SendAdr, SendCnt, SendDat, SendWait);
    type   bus16 is array(15 downto 0) of std_logic;
end Define;