v2_6.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;

package arith is
	function max(L, R: std_logic_vector) return std_logic_vector;
end arith;

library ieee;
use ieee.std_logic_signed.all;

package body arith is

	function max(L, R: std_logic_vector) return std_logic_vector is
	begin
		if L > R then
	    	return L;
		else
	    	return R;
		end if;
	end function;

end arith;

library ieee;
use ieee.std_logic_1164.all;
use work.arith.all;

entity V2_6 is
 port(a  : in  std_logic_vector(7 downto 0);
      b  : in  std_logic_vector(7 downto 0);
      o  : out std_logic_vector(7 downto 0));
end V2_6;

architecture a of V2_6 is
begin
	o <= max(a,b);	
end a;