v7_5.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V7_5 is 
	port(a1  	: in   std_logic_vector(7 downto 0);
	    b1  : in   std_logic_vector(7 downto 0);
	    c1  : out  std_logic_vector(7 downto 0);
	    a2  	: in   bit_vector(7 downto 0);
	    b2  : in   bit_vector(7 downto 0);
	    c2  : out  bit_vector(7 downto 0);
	    c3  : out  std_logic_vector(7 downto 0));
end V7_5;

architecture A of V7_5 is	

	function bit2std(Inb : bit_vector; shift : integer ) return
	         std_logic_vector is	
	    variable tempTrans : std_logic_vector(shift - 1 downto 0);         
	begin
		for i in 0 to shift - 1 loop
			if Inb(i) = '0' then
				tempTrans(i) := '0';
			else
				tempTrans(i) := '1';
			end if;
		end loop;
		return tempTrans;
	end function;

	function max(Ina : std_logic_vector; Inb : std_logic_vector) return
	         std_logic_vector is	         
	begin
		if Inb > Ina then
			return Inb;
		else
			return Ina;
		end if;
	end function;

	function max(Ina : bit_vector; Inb : bit_vector) return
	         bit_vector is	         
	begin
		if Inb > Ina then
			return Inb;
		else
			return Ina;
		end if;
	end function;

	function max(Ina : bit_vector; Inb : bit_vector) return
	         std_logic_vector is	         
	begin
		if Inb > Ina then
			return bit2std(Inb,8);
		else
			return bit2std(Ina,8);
		end if;
	end function;

begin
	
	c1 <= max(a1,b1);
	c2 <= max(a2,b2);
	c3 <= max(a2,b2);
	
end A;