v7_3.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee. numeric_std.all;

entity V7_3 is 
	port(a   	: in  std_logic_vector(7 downto 0);
	     b  	: in  bit_vector(7 downto 0);
	     c1     : out std_logic_vector(7 downto 0);
	     c2     : out std_logic_vector(7 downto 0));
end V7_3;

architecture A of V7_3 is	

	function bit2std(Inb : bit_vector; shift : integer ) return
	         std_logic_vector is	
	    variable tempTrans : std_logic_vector(shift - 1 downto 0);         
	begin
		for i in 0 to shift - 1 loop
			if Inb(i) = '0' then
				tempTrans(i) := '0';
			else
				tempTrans(i) := '1';
			end if;
		end loop;
		return tempTrans;
	end function;
  
	constant shiftc : integer := 3;

begin
	
	c1 <= std_logic_vector (SHIFT_LEFT(unsigned(a),shiftc));
	c2 <= std_logic_vector (SHIFT_LEFT(unsigned(bit2std(b,8)),shiftc));
	
end A;