v7_1.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V7_1 is 
	port(a,b : in  bit;
	     c   : out std_logic);
end V7_1;

architecture a of V7_1 is

	function bit2std(Inb : bit ) return
	         std_logic is	         
	begin
		if Inb = '0' then
			return '0';
		else
			return '1';
		end if;
	end function;
	
	signal bitc : bit;

begin
	
	bitc <= a and b;
	c <= bit2std(bitc);
	
end  a;