v7_7.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;

entity TProc is
    port(a  : in std_logic;
        b  : inout std_logic;
        o  : out std_logic);
end TProc; 

architecture A_TProc of TProc is

    procedure TP(InA 		: in std_logic;
                InB 	: inout std_logic;
                OutO 	: out std_logic;
                OE   	: in std_logic := '1';
                Flag 	: in boolean := FALSE) is
    begin
        if Flag then
            OutO := InA;
        else
            OutO := InB;
        end if;
        if OE = '0' then
            InB := InA;
        end if;
    end;               
                 
begin
     
    process(a,b)
        variable OutO : std_logic;
        variable WInB : std_logic;  
        variable Flag  : boolean;  
    begin
        WInB := b;
        TP(a,WInB,OutO);  
        b <= WInB;
        o <= OutO;
    end process; 
    
end A_TProc;