v7_4.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V7_4 is 
	port( a1  	: in   std_logic_vector(7 downto 0);
	     b1  	: in   std_logic_vector(7 downto 0);
	     c1     : out  std_logic_vector(7 downto 0);
	     a2  	: in   bit_vector(7 downto 0);
	     b2  	: in   bit_vector(7 downto 0);
	     c2     : out  bit_vector(7 downto 0));
end V7_4;

architecture A of V7_4 is	

	function max(Ina : std_logic_vector; Inb : std_logic_vector) return
	         std_logic_vector is	         
	begin
		if Inb > Ina then
			return Inb;
		else
			return Ina;
		end if;
	end function;

	function max(Ina : bit_vector; Inb : bit_vector) return
	         bit_vector is	         
	begin
		if Inb > Ina then
			return Inb;
		else
			return Ina;
		end if;
	end function;

begin
	
	c1 <= max(a1,b1);
	c2 <= max(a2,b2);
	
end A;