v7_2.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity V7_2 is 
	port(a  	: in  std_logic_vector(7 downto 0);
	     b  	: in  bit_vector(7 downto 0);
	     c1     : out std_logic_vector(7 downto 0);
	     c2     : out std_logic_vector(7 downto 0));
end V7_2;

architecture A of V7_2 is	
  
	constant shiftc : integer := 3;

begin
	
	c1 <= std_logic_vector (SHIFT_LEFT(unsigned(a),shiftc));
	c2 <= std_logic_vector (SHIFT_LEFT(unsigned(b),shiftc));
	
end A;