udasyncounter.map.qmsg

Up-down Asynchronous counter in Behavioral Model

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 18 13:28:41 2007 " "Info: Processing started: Thu Oct 18 13:28:41 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UDasyncounter -c UDasyncounter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UDasyncounter -c UDasyncounter" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UDasyncounter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UDasyncounter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UDasyncounter-beh " "Info: Found design unit 1: UDasyncounter-beh" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 UDasyncounter " "Info: Found entity 1: UDasyncounter" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UDasyncounter " "Info: Elaborating entity \"UDasyncounter\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Error" "EVRFX_VDB_REG_MATCHES_NO_TEMPLATE" "Q\[0\] UDasyncounter.vhd(16) " "Error (10821): HDL error at UDasyncounter.vhd(16): can't infer register for \"Q\[0\]\" because its behavior does not match any supported register model" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 16 0 0 } }  } 0 10821 "HDL error at %2!s!: can't infer register for \"%1!s!\" because its behavior does not match any supported register model" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "Q\[0\] UDasyncounter.vhd(12) " "Info (10041): Inferred latch for \"Q\[0\]\" at UDasyncounter.vhd(12)" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Error" "EVRFX_VDB_REG_MATCHES_NO_TEMPLATE" "Q\[1\] UDasyncounter.vhd(16) " "Error (10821): HDL error at UDasyncounter.vhd(16): can't infer register for \"Q\[1\]\" because its behavior does not match any supported register model" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 16 0 0 } }  } 0 10821 "HDL error at %2!s!: can't infer register for \"%1!s!\" because its behavior does not match any supported register model" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "Q\[1\] UDasyncounter.vhd(12) " "Info (10041): Inferred latch for \"Q\[1\]\" at UDasyncounter.vhd(12)" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Error" "EVRFX_VDB_REG_MATCHES_NO_TEMPLATE" "Q\[2\] UDasyncounter.vhd(16) " "Error (10821): HDL error at UDasyncounter.vhd(16): can't infer register for \"Q\[2\]\" because its behavior does not match any supported register model" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 16 0 0 } }  } 0 10821 "HDL error at %2!s!: can't infer register for \"%1!s!\" because its behavior does not match any supported register model" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "Q\[2\] UDasyncounter.vhd(12) " "Info (10041): Inferred latch for \"Q\[2\]\" at UDasyncounter.vhd(12)" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Error" "EVRFX_VDB_REG_MATCHES_NO_TEMPLATE" "Q\[3\] UDasyncounter.vhd(16) " "Error (10821): HDL error at UDasyncounter.vhd(16): can't infer register for \"Q\[3\]\" because its behavior does not match any supported register model" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 16 0 0 } }  } 0 10821 "HDL error at %2!s!: can't infer register for \"%1!s!\" because its behavior does not match any supported register model" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "Q\[3\] UDasyncounter.vhd(12) " "Info (10041): Inferred latch for \"Q\[3\]\" at UDasyncounter.vhd(12)" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "UDasyncounter.vhd(17) " "Error (10822): HDL error at UDasyncounter.vhd(17): couldn't implement registers for assignments on this clock edge" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 17 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "UDasyncounter.vhd(20) " "Error (10822): HDL error at UDasyncounter.vhd(20): couldn't implement registers for assignments on this clock edge" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 20 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "UDasyncounter.vhd(23) " "Error (10822): HDL error at UDasyncounter.vhd(23): couldn't implement registers for assignments on this clock edge" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 23 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "UDasyncounter.vhd(26) " "Error (10822): HDL error at UDasyncounter.vhd(26): couldn't implement registers for assignments on this clock edge" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 26 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "UDasyncounter.vhd(30) " "Error (10822): HDL error at UDasyncounter.vhd(30): couldn't implement registers for assignments on this clock edge" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 30 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "UDasyncounter.vhd(33) " "Error (10822): HDL error at UDasyncounter.vhd(33): couldn't implement registers for assignments on this clock edge" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 33 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "UDasyncounter.vhd(36) " "Error (10822): HDL error at UDasyncounter.vhd(36): couldn't implement registers for assignments on this clock edge" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 36 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "UDasyncounter.vhd(39) " "Error (10822): HDL error at UDasyncounter.vhd(39): couldn't implement registers for assignments on this clock edge" {  } { { "UDasyncounter.vhd" "" { Text "E:/VHDL programs/UDasyncounter/UDasyncounter.vhd" 39 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 13 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 13 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 18 13:28:54 2007 " "Error: Processing ended: Thu Oct 18 13:28:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:13 " "Error: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}