📄 udasyncounter.vhd
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library ieee;
use ieee.std_logic_1164.all;
Entity UDasyncounter is
port (ud,reset,clk : in bit; Z : out bit_vector(3 downto 0));
end UDasyncounter;
Architecture beh of UDasyncounter is
signal Q : bit_vector(3 downto 0);
begin
-- Q <= "0000";
process(ud,reset,clk,Q)
begin
if reset = '1' then Q <= "0000";
else
if ud = '0' then
if clk'event and clk = '0' then
Q(0) <= not Q(0);
end if;
if Q(0)'event and Q(0) = '0' then
Q(1) <= not Q(1);
end if;
if Q(1)'event and Q(1) = '0' then
Q(2) <= not Q(2);
end if;
if Q(2)'event and Q(2) = '0' then
Q(3) <= not Q(3);
end if;
else
if clk'event and clk = '1' then
Q(0) <= not Q(0);
end if;
if Q(0)'event and Q(0) = '1' then
Q(1) <= not Q(1);
end if;
if Q(1)'event and Q(1) = '1' then
Q(2) <= not Q(2);
end if;
if Q(2)'event and Q(2) = '1' then
Q(3) <= not Q(3);
end if;
end if;
end if;
end process;
Z <= Q;
end beh;
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