udasyncounter.vho

Up-down Asynchronous counter in Behavioral Model

-- pragma translate_on
PORT MAP (
	pathsel => \Q[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => VCC,
	datab => \Q[0]\,
	datac => \Q~8\,
	datad => VCC,
	aclr => \reset~combout\,
	aload => \ALT_INV_ud~combout\,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Q[0]~I_modesel\,
	regout => \Q[0]\);

\Q~0_I\ : cyclone_lcell
-- Equation(s):
-- \Q~0\ = DFFEAS(!\Q[1]\, !GLOBAL(\Q[0]\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0F0F",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Q~0_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \ALT_INV_Q[0]\,
	dataa => VCC,
	datab => VCC,
	datac => \Q[1]\,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Q~0_I_modesel\,
	regout => \Q~0\);

\Q[1]~I\ : cyclone_lcell
-- Equation(s):
-- \Q[1]\ = DFFEAS(!\Q[1]\, GLOBAL(\Q[0]\), !GLOBAL(\reset~combout\), , , \Q~0\, !GLOBAL(\ud~combout\), , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "5555",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Q[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \Q[0]\,
	dataa => \Q[1]\,
	datab => VCC,
	datac => \Q~0\,
	datad => VCC,
	aclr => \reset~combout\,
	aload => \ALT_INV_ud~combout\,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Q[1]~I_modesel\,
	regout => \Q[1]\);

\Q~1_I\ : cyclone_lcell
-- Equation(s):
-- \Q~1\ = DFFEAS(!\Q[2]\, !GLOBAL(\Q[1]\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0F0F",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Q~1_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \ALT_INV_Q[1]\,
	dataa => VCC,
	datab => VCC,
	datac => \Q[2]\,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Q~1_I_modesel\,
	regout => \Q~1\);

\Q[2]~I\ : cyclone_lcell
-- Equation(s):
-- \Q[2]\ = DFFEAS(!\Q[2]\, GLOBAL(\Q[1]\), !GLOBAL(\reset~combout\), , , \Q~1\, !GLOBAL(\ud~combout\), , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "5555",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Q[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \Q[1]\,
	dataa => \Q[2]\,
	datab => VCC,
	datac => \Q~1\,
	datad => VCC,
	aclr => \reset~combout\,
	aload => \ALT_INV_ud~combout\,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Q[2]~I_modesel\,
	regout => \Q[2]\);

\Q~2_I\ : cyclone_lcell
-- Equation(s):
-- \Q~2\ = DFFEAS(!\Q[3]\, !GLOBAL(\Q[2]\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0F0F",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Q~2_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \ALT_INV_Q[2]\,
	dataa => VCC,
	datab => VCC,
	datac => \Q[3]\,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Q~2_I_modesel\,
	regout => \Q~2\);

\Q[3]~I\ : cyclone_lcell
-- Equation(s):
-- \Q[3]\ = DFFEAS(!\Q[3]\, GLOBAL(\Q[2]\), !GLOBAL(\reset~combout\), , , \Q~2\, !GLOBAL(\ud~combout\), , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "3333",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Q[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \Q[2]\,
	dataa => VCC,
	datab => \Q[3]\,
	datac => \Q~2\,
	datad => VCC,
	aclr => \reset~combout\,
	aload => \ALT_INV_ud~combout\,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Q[3]~I_modesel\,
	regout => \Q[3]\);

\Z[0]~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \Q[0]\,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \Z[0]~I_modesel\,
	padio => ww_Z(0));

\Z[1]~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \Q[1]\,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \Z[1]~I_modesel\,
	padio => ww_Z(1));

\Z[2]~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \Q[2]\,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \Z[2]~I_modesel\,
	padio => ww_Z(2));

\Z[3]~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \Q[3]\,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \Z[3]~I_modesel\,
	padio => ww_Z(3));
END structure;