udasyncounter.vho

Up-down Asynchronous counter in Behavioral Model

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Web Edition"

-- DATE "10/10/2007 15:59:14"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	UDasyncounter IS
    PORT (
	ud : IN std_logic;
	reset : IN std_logic;
	clk : IN std_logic;
	Z : OUT std_logic_vector(3 DOWNTO 0)
	);
END UDasyncounter;

ARCHITECTURE structure OF UDasyncounter IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_ud : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_Z : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \Q~8_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Q~8_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \reset~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \ud~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \Q[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Q[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Q~0_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Q~0_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Q[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Q[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Q~1_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Q~1_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Q[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Q[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Q~2_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Q~2_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Q[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \Q[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Z[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \Z[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \Z[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \Z[3]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \clk~combout\ : std_logic;
SIGNAL \Q~8\ : std_logic;
SIGNAL \reset~combout\ : std_logic;
SIGNAL \ud~combout\ : std_logic;
SIGNAL \Q[0]\ : std_logic;
SIGNAL \Q~0\ : std_logic;
SIGNAL \Q[1]\ : std_logic;
SIGNAL \Q~1\ : std_logic;
SIGNAL \Q[2]\ : std_logic;
SIGNAL \Q~2\ : std_logic;
SIGNAL \Q[3]\ : std_logic;
SIGNAL \ALT_INV_Q[0]\ : std_logic;
SIGNAL \ALT_INV_Q[1]\ : std_logic;
SIGNAL \ALT_INV_Q[2]\ : std_logic;
SIGNAL \ALT_INV_clk~combout\ : std_logic;
SIGNAL \ALT_INV_ud~combout\ : std_logic;
COMPONENT cyclone_lcell
PORT (
	clk : IN STD_LOGIC;
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cin0 : IN STD_LOGIC;
	cin1 : IN STD_LOGIC;
	inverta : IN STD_LOGIC;
	regcascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cout0 : OUT STD_LOGIC;
	cout1 : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	enable_asynch_arcs : IN STD_LOGIC);
END COMPONENT;

COMPONENT cyclone_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(26 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_ud <= ud;
ww_reset <= reset;
ww_clk <= clk;
Z <= ww_Z;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\clk~I_modesel\ <= "000000000000000000000000001";
\Q~8_I_modesel\ <= "1100001010101";
\Q~8_I_pathsel\ <= "00000000100";
\reset~I_modesel\ <= "000000000000000000000000001";
\ud~I_modesel\ <= "000000000000000000000000001";
\Q[0]~I_modesel\ <= "1100001010101";
\Q[0]~I_pathsel\ <= "00000000010";
\Q~0_I_modesel\ <= "1100001010101";
\Q~0_I_pathsel\ <= "00000000100";
\Q[1]~I_modesel\ <= "1100001010101";
\Q[1]~I_pathsel\ <= "00000000001";
\Q~1_I_modesel\ <= "1100001010101";
\Q~1_I_pathsel\ <= "00000000100";
\Q[2]~I_modesel\ <= "1100001010101";
\Q[2]~I_pathsel\ <= "00000000001";
\Q~2_I_modesel\ <= "1100001010101";
\Q~2_I_pathsel\ <= "00000000100";
\Q[3]~I_modesel\ <= "1100001010101";
\Q[3]~I_pathsel\ <= "00000000010";
\Z[0]~I_modesel\ <= "000000000000000000000000010";
\Z[1]~I_modesel\ <= "000000000000000000000000010";
\Z[2]~I_modesel\ <= "000000000000000000000000010";
\Z[3]~I_modesel\ <= "000000000000000000000000010";

\INV_INST_Q[0]\ : INV
PORT MAP (
	 IN1 => \Q[0]\,
	 Y => \ALT_INV_Q[0]\);

\INV_INST_Q[1]\ : INV
PORT MAP (
	 IN1 => \Q[1]\,
	 Y => \ALT_INV_Q[1]\);

\INV_INST_Q[2]\ : INV
PORT MAP (
	 IN1 => \Q[2]\,
	 Y => \ALT_INV_Q[2]\);

\INV_INST_clk~combout\ : INV
PORT MAP (
	 IN1 => \clk~combout\,
	 Y => \ALT_INV_clk~combout\);

\INV_INST_ud~combout\ : INV
PORT MAP (
	 IN1 => \ud~combout\,
	 Y => \ALT_INV_ud~combout\);

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

\clk~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \clk~I_modesel\,
	combout => \clk~combout\,
	padio => ww_clk);

\Q~8_I\ : cyclone_lcell
-- Equation(s):
-- \Q~8\ = DFFEAS(!\Q[0]\, !GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0F0F",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \Q~8_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \ALT_INV_clk~combout\,
	dataa => VCC,
	datab => VCC,
	datac => \Q[0]\,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Q~8_I_modesel\,
	regout => \Q~8\);

\reset~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \reset~I_modesel\,
	combout => \reset~combout\,
	padio => ww_reset);

\ud~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \ud~I_modesel\,
	combout => \ud~combout\,
	padio => ww_ud);

\Q[0]~I\ : cyclone_lcell
-- Equation(s):
-- \Q[0]\ = DFFEAS(!\Q[0]\, GLOBAL(\clk~combout\), !GLOBAL(\reset~combout\), , , \Q~8\, !GLOBAL(\ud~combout\), , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "3333",
--	output_mode => "reg_only")