udasyncounter_vhd.sdo

Up-down Asynchronous counter in Behavioral Model

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This SDF file should be used for PrimeTime (VHDL) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "UDasyncounter")
  (DATE "10/10/2007 15:59:14")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 5.1 Build 176 10/26/2005 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\clk\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Q\~8_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (551:551:551) (551:551:551))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\Q\~8_I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1029:1029:1029) (1029:1029:1029))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\Q\~8_I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1457:1457:1457) (1457:1457:1457))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\reset\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\ud\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Q\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (513:513:513) (513:513:513))
        (PORT datac (537:537:537) (537:537:537))
        (IOPATH datab regin (607:607:607) (607:607:607))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\Q\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aload (1316:1316:1316) (1316:1316:1316))
        (PORT adata (537:537:537) (537:537:537))
        (PORT aclr (1644:1644:1644) (1644:1644:1644))
        (PORT clk (1457:1457:1457) (1457:1457:1457))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
        (IOPATH (posedge aload) regout (956:956:956) (956:956:956))
        (IOPATH adata regout (370:370:370) (370:370:370))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Q\~0_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (556:556:556) (556:556:556))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\Q\~0_I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1034:1034:1034) (1034:1034:1034))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\Q\~0_I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4211:4211:4211) (4211:4211:4211))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Q\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (540:540:540) (540:540:540))
        (PORT datac (549:549:549) (549:549:549))
        (IOPATH dataa regin (738:738:738) (738:738:738))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\Q\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aload (1292:1292:1292) (1292:1292:1292))
        (PORT adata (549:549:549) (549:549:549))
        (PORT aclr (1624:1624:1624) (1624:1624:1624))
        (PORT clk (4211:4211:4211) (4211:4211:4211))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
        (IOPATH (posedge aload) regout (956:956:956) (956:956:956))
        (IOPATH adata regout (370:370:370) (370:370:370))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Q\~1_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (550:550:550) (550:550:550))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\Q\~1_I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1028:1028:1028) (1028:1028:1028))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\Q\~1_I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4771:4771:4771) (4771:4771:4771))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Q\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (535:535:535) (535:535:535))
        (PORT datac (538:538:538) (538:538:538))
        (IOPATH dataa regin (738:738:738) (738:738:738))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\Q\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aload (1339:1339:1339) (1339:1339:1339))
        (PORT adata (538:538:538) (538:538:538))
        (PORT aclr (1662:1662:1662) (1662:1662:1662))
        (PORT clk (4771:4771:4771) (4771:4771:4771))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
        (IOPATH (posedge aload) regout (956:956:956) (956:956:956))
        (IOPATH adata regout (370:370:370) (370:370:370))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Q\~2_I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (551:551:551) (551:551:551))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE \\Q\~2_I\\.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (1029:1029:1029) (1029:1029:1029))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\Q\~2_I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4937:4937:4937) (4937:4937:4937))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\Q\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (513:513:513) (513:513:513))
        (PORT datac (537:537:537) (537:537:537))
        (IOPATH datab regin (607:607:607) (607:607:607))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\Q\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aload (1279:1279:1279) (1279:1279:1279))
        (PORT adata (537:537:537) (537:537:537))
        (PORT aclr (1624:1624:1624) (1624:1624:1624))
        (PORT clk (4937:4937:4937) (4937:4937:4937))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
        (IOPATH (posedge aload) regout (956:956:956) (956:956:956))
        (IOPATH adata regout (370:370:370) (370:370:370))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\Z\[0\]\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (2193:2193:2193) (2193:2193:2193))
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\Z\[1\]\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1886:1886:1886) (1886:1886:1886))
        (IOPATH datain padio (2108:2108:2108) (2108:2108:2108))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\Z\[2\]\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (3335:3335:3335) (3335:3335:3335))
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\Z\[3\]\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1144:1144:1144) (1144:1144:1144))
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
)